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A high-speed burst signal synchronization and equalization device and method

A burst signal, equalization device technology, applied in the field of optical access, to achieve high equalization and peak/valley detection efficiency, ensure payload bandwidth, and improve the effect of quality

Active Publication Date: 2021-09-21
FENGHUO COMM SCI & TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the adaptive update method based on the training sequence is used, the key problem is to locate the relative position of PSBu in the burst signal

Method used

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  • A high-speed burst signal synchronization and equalization device and method
  • A high-speed burst signal synchronization and equalization device and method
  • A high-speed burst signal synchronization and equalization device and method

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Experimental program
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Embodiment 1

[0058] see figure 2 As shown, this embodiment provides a high-speed burst signal synchronization and equalization device, including an equalizer, a time synchronizer and an equalization controller.

[0059] Wherein, the equalizer is used to: receive the uplink burst signal, and under the control of the equalization controller, transmit the calculated equalized output to the time synchronizer in the blind equalization mode or the training equalization mode; wherein, the uplink burst The signaled PSBu data pattern includes two parts, A+ and A-, and A+ and A- are negatively correlated. For example, taking the 32-bit PSBu data mode as an example, if the A+ part is expressed in binary as: [1,1,-1,1,-1,-1,1,-1,1,1,1,- 1,1,1,1,-1], then the A-part is expressed in binary as: [-1,-1,1,-1,1,1,-1,1,-1,-1,-1 ,1,-1,-1,-1,1]. It can be understood that the PSBu data pattern designed above has good autocorrelation characteristics, which is convenient for the time synchronizer to effective...

Embodiment 2

[0085] A high-speed burst signal synchronization and equalization device provided by this embodiment has the same basic structure as that of Embodiment 1, the difference being that this embodiment takes the 32-bit PSBu data mode as an example, as shown in Table 1. The A+ part of the PSBu data pattern is preferably expressed in binary as: [1,1,-1,1,-1,-1,1,-1,1,1,1,-1,1,1,1,- 1], then the A-part is preferably expressed in binary as: [-1,-1,1,-1,1,1,-1,1,-1,-1,-1,1,-1,-1 ,-1,1].

[0086] Table 1: 32-bit PSBu data pattern

[0087] Inx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bit 1 1 -1 1 -1 -1 1 -1 1 1 1 -1 1 1 1 -1 Inx 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bit -1 -1 1 -1 1 1 -1 1 -1 -1 -1 1 -1 -1 -1 1

[0088] Based on the 32-bit PSBu data pattern in above-mentioned table 1, construct PSBu and local data pattern (refer to image 3 shown), and then carry out a correlation opera...

Embodiment 3

[0091] A high-speed burst signal synchronization and equalization device provided by this embodiment has the same basic structure as Embodiment 1, the difference is that this embodiment takes the 64-bit PSBu data mode as an example, as shown in Table 2, The A+ part of the PSBu data pattern is preferably expressed in binary as: [1,-1,1,-1,-1,-1,1,1,-1,1,1,1,-1,-1,1 ,1,1,1,-1,-1,1,-1,1,1,-1,-1,1,-1,1,-1,-1,-1], then A-part is preferred Expressed in binary as: [-1,1,-1,1,1,1,-1,-1,1,-1,-1,-1,1,1,-1,-1,-1, -1,1,1,-1,1,-1,-1,1,1,-1,1,-1,1,1,1].

[0092]Table 2: 64-bit PSBu data pattern

[0093] Inx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 bit 1 -1 1 -1 -1 -1 1 1 -1 1 1 1 -1 -1 1 1 Inx 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bit 1 1 -1 -1 1 -1 1 1 -1 -1 1 -1 1 -1 -1 -1 Inx 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 bit -1 1 -1 1 1 1 -1 -1 1 -1 -1...

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Abstract

The invention discloses a high-speed burst signal synchronization and equalization device and method, and relates to the technical field of optical access. The device includes an equalizer, a time synchronizer and an equalization controller. The equalizer receives the uplink burst signal, and under the control of the equalizer controller, transmits the calculated equalized output to the time synchronizer in the blind equalization mode or the training equalization mode. Wherein, the PSBu data pattern of the uplink burst signal includes two parts, A+ and A-, which are negatively correlated. The time synchronizer finds the uplink burst signal based on the PSBu data mode, performs boundary identification, and feeds back to the equalizer controller. The equalization controller controls the equalizer to switch between the blind equalization mode and the training equalization mode according to the preset equalization control state machine according to the feedback. The present invention effectively combines the advantages of the two equalization modes, not only can efficiently equalize but also effectively guarantee the payload bandwidth of the system, and can also improve the quality of synchronization and training to meet the actual application requirements.

Description

technical field [0001] The invention relates to the field of optical access technology, in particular to a high-speed burst signal synchronization and equalization device and method. Background technique [0002] TDM-PON (Time Division Multiplexing-Passive Optical Network, Time Division Multiplexing-Passive Optical Network) is a passive optical network that uses time-division multiplexing as an access technology. In the TDM-PON system, the data frame structure of the uplink burst signal usually includes two parts: PSBu (UpLink Physical Synchronization Block, uplink physical synchronization block) and Payload (data payload), such as figure 1 shown. Among them, the function of PSBu is to discover the uplink burst signal and synchronize. After synchronization, the system can precisely locate the payload and extract the frame data. [0003] However, as the transmission rate increases, for example, the code rate increases to 50GBaud and above, the synchronization of the upstre...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L25/03H04Q11/00H04J3/06
CPCH04J3/0685H04L25/03006H04L2025/03598H04L2025/03726H04Q11/0067
Inventor 胡荣王志军
Owner FENGHUO COMM SCI & TECH CO LTD
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