Tensor cache and access structure and method thereof

Abstract

The invention provides a Tensor cache, an access structure and a method thereof. The method comprises the following steps: S1, acquiring a mapping relationship between Tensor structure variables of the Tensor cache and an incidence matrix; S2, executing a) or b) according to the mapping relationship: a) loading the data of the incidence matrix in the main memory into a Tensor cache; and b) writing the data in the Tensor cache into the incidence matrix in the main memory. According to the scheme, the data of the incidence matrix in the main memory is mapped and extracted into the Tensor cache chip, and the data of the incidence matrix is cut and respectively placed in different cache chips, so that subsequent data conversion and parallel operation are facilitated, and meanwhile, the utilization rate of a limited on-chip memory can be improved; distributing the data of the Tensor cache in a multi-dimensional manner, and processing the data in a multi-dimensional manner, so that the data processing efficiency can be effectively improved, and the problem of memory bank access conflicts can be effectively avoided; realizing cache access and parallel processing of data, and avoiding the problems of waste of on-chip storage space and inconsistent data access delay.

Description

technical field [0001] The invention belongs to the technical field of data cache and access, and in particular relates to a Tensor cache and an access method. Background technique [0002] Algorithms such as deep learning and image processing have the characteristics of memory access and regular calculation. At present, there are three main ways to cache and access data for algorithms such as deep learning and image processing: [0003] 1) Private Cache, shared address space [0004] 2) Independent sticky note memory [0005] 3) Shared Cache [0006] However, in the case of shared Cache, using multiple computing engines for processing is likely to cause problems such as complex memory access scheduling and storage bank access conflicts. However, when using a private cache / separate scratch pad memory, since there are multiple copies of the same data on-chip, it will lead to waste of limited on-chip storage space and inconsistent data access delays. Contents of the inven...

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Problems solved by technology

[0006] However, in the case of shared Cache, using multiple computing engines for processing is prone to problems such as complex memory access scheduling and storage bank access conflicts.

However, when using private cache / separate scratch pad memory, since there are multiple copies of the same data on the chip, it will lead to waste of limited on-chip storage space and inconsistent data access delays.

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