Graphical secondary development method of eda software in chip layout design

A layout design and secondary development technology, applied in CAD circuit design, visual/graphic programming, computer-aided design, etc., to achieve the effect of speeding up, improving flexibility, and reducing operation complexity

Active Publication Date: 2021-08-13
BATELAB CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In order to overcome the above-mentioned deficiencies in the prior art, the purpose of the present invention is to propose a graphical secondary development method of EDA software in chip layout design, to solve the problems of easy-to-handle operation and optimized efficiency of the software

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  • Graphical secondary development method of eda software in chip layout design

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Embodiment Construction

[0017] The specific implementation of the present invention will be described in further detail below in conjunction with the accompanying drawings of the embodiments, so as to make the technical solution of the present invention easier to understand and grasp, so as to define the protection scope of the present invention more clearly.

[0018] Aiming at many existing deficiencies, the designer of the present invention relies on long-term experience in chip design such as analog integrated circuits, and innovatively proposes a graphical secondary development method of EDA software in chip layout design, which is vivid, specific, and visualized. And the logical graphic editing method replaces the simple text input and editing in the past, and solves the problem of easy-to-use operation and optimized efficiency of chip layout design.

[0019] The above-mentioned graphical secondary development method of the present invention is implemented based on the system function call provid...

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Abstract

The invention discloses a graphical secondary development method of EDA software in chip layout design. In the process of chip layout design, the text program to be edited is converted into the association between several nodes, and graphically converted into a flow chart, which includes the flow chart drawing interface, program variables to be selected and program function modules to be selected under the visual interface of the computer In their respective areas, developers update the flow chart by calling function modules to add new nodes, and assign value nodes through variables until the flow chart is complete; the flow chart and all the variables in it are presented in sub-regions under the visual interface of the computer, and the process The graph shows a set of inputs, displays the output results in real time and analyzes the nodes that cause gaps relative to the expected goals, and adjusts the variable assignments of some nodes to make the output results approach the expected goals. The method of the invention is beneficial to reduce the operation complexity of the chip layout design and improve the design efficiency, and the interactive interface is intuitive and friendly, and the debugging is simple and convenient.

Description

technical field [0001] The invention relates to the field of semiconductor chip design, in particular to a technical solution for computer-aided chip layout design and graphic secondary development of existing EDA software. Background technique [0002] With the rapid development of smart terminal equipment, everything from small data adapters and Bluetooth headsets to large control systems for cars, ships, and airplanes cannot do without high-precision designed and processed semiconductor chips. Over the years, computer software technology has also made great breakthroughs. Among them, almost all EDA software supports secondary development as automatic devices to accelerate chip layout design. [0003] In a common development case, it is known that the capacitance value of 1μm×1μm is 0.02pF under a specific process. In order to obtain a capacitor of 1pF, the developer can manually draw a capacitor of 4μm×25μm, or draw a capacitor of 7μm×7μm capacitance (with a 2% error). ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F8/34G06F30/31G06F30/392G06F117/08
CPCG06F8/34G06F30/31G06F30/392G06F2117/08
Inventor 李真
Owner BATELAB CO LTD
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