Preparation method of semiconductor structure
A semiconductor and buffer layer technology, which is applied in the field of semiconductor structure preparation, can solve the problem of inconsistency in the size of etching holes, and achieve the effect of uniform size
Active Publication Date: 2021-06-22
CHANGXIN MEMORY TECH INC
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[0004] Based on this, it is necessary to provide a method for preparing a semiconductor structure for the problem of inconsistent etching hole sizes in the prior art
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[0073] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. A preferred embodiment of the application is shown in the drawings. However, the present application can be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive.
[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application.
[0075] It will be understood that when an element or layer is referred to as being "on," "adjac...
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Abstract
The invention relates to a preparation method of a semiconductor structure. The preparation method comprises the steps of forming a first mask layer, a first buffer layer, a second mask layer and a second buffer layer which are sequentially stacked from bottom to top, wherein the etching selection ratio of the second buffer layer to the first buffer layer is greater than 1; patterning the second buffer layer and the second mask layer; forming a first mask pattern on the side wall of the first pattern, wherein the first mask pattern extends along the first direction; removing the second buffer layer and the second mask layer; forming a third mask layer, a third buffer layer, a fourth mask layer and a fourth buffer layer which are sequentially stacked from bottom to top, wherein the etching selection ratio of the fourth buffer layer to the third buffer layer is greater than 1; patterning the fourth buffer layer and the fourth mask layer; forming a second mask pattern on the side wall of the second pattern, wherein the second mask pattern extends in the second direction, and the second direction is obliquely crossed with the first direction; and removing the fourth buffer layer and the fourth mask layer. The sizes of the etching holes formed by the preparation method of the semiconductor structure are consistent, and the performance of the device is not affected.
Description
technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a method for preparing a semiconductor structure. Background technique [0002] With the development of semiconductor technology, it is usually necessary to form two layers of mask patterns in the existing semiconductor structure. The two layers of mask patterns both include grooves arranged at intervals. And viewed from a top view, the two layers of mask patterns are oblique to each other. The two layers of mask patterns are transferred to the target mask layer, thereby defining the pattern of etching holes on the material to be etched. [0003] However, since the underlying material is easily etched when forming the mask pattern, after the two layers of mask patterns are transferred to the target mask layer, the size of the hole formed by the intersection of the two layers of mask patterns on the target mask layer is not large. uniform. Therefore, when...
Claims
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Login to View More IPC IPC(8): H01L21/308
CPCH01L21/3086
Inventor 曹新满刘忠明白世杰
Owner CHANGXIN MEMORY TECH INC