[0021] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.
[0022] For a traditional image sensor, a column of pixel units shares one CTIA, which leads to an excessively long column bus, which makes the parasitic capacitance of the CTIA input too large, and the noise of the CTIA is too large, which will reduce the signal-to-noise ratio of the CMOS image sensor and affect the imaging effect. In order to avoid the problem that the column bus is too long, the present invention adopts the method of segmental control and driving of pixels, and divides a pixel into several segments for driving, each segment is equivalent to a sub-pixel unit, and each sub-pixel unit is respectively configured with a CTIA , thereby shortening the length of the column bus, making the capacitance of the CTIA input terminal very small, and making the output noise of the CTIA very small, thereby improving the signal-to-noise ratio of the image sensor and improving the imaging effect.
[0023] In the present invention, a pixel can be divided into a plurality of sub-pixel units with the same structure. The following is an example of dividing a pixel into two sub-pixel units, and the same can be obtained by dividing into more sub-pixel units.
[0024] figure 1 The overall architecture of an image sensor according to one embodiment of the present invention is shown.
[0025] like figure 1 As shown, the image sensor includes a CTIA pixel readout structure and a pixel readout circuit, the CTIA pixel readout structure includes two sub-pixel units 1 with the same structure, and the two sub-pixel units 1 are respectively equipped with CTIA2, so that the two sub-pixel units 1 are respectively The CTIA pixel structure is formed, and the two sub-pixel units 1 are respectively driven at the same time and output synchronously.
[0026] figure 2 The architecture of a sub-pixel unit according to one embodiment of the present invention is shown.
[0027] like figure 2 As shown, the sub-pixel unit includes a charge exposure and transfer structure and CTIA, the charge exposure and transfer structure is used to realize the exposure, storage and transfer of charges, and the CTIA is used to integrate and amplify the signal output by the charge exposure and transfer structure.
[0028] The charge exposure transfer structure includes a pixel reset transistor GRST, a photodiode PD, a first charge transfer transistor TX1, a second charge transfer transistor TX2, a storage diode MN, a floating diffusion node reset transistor RST, and a floating diffusion node FD,
[0029] The source of the pixel reset transistor GRST is connected to the supply voltage, the drain of the pixel reset transistor GRST is coupled to the source of the first charge transfer transistor TX1, the drain of the first charge transfer transistor TX1 and the source of the second charge transfer transistor TX2 The drain of the second charge transfer transistor TX2 is coupled to the floating diffusion node FD, the source of the floating diffusion node reset transistor RST is connected to the supply voltage, and the drain of the floating diffusion node reset transistor RST is coupled to the floating diffusion node FD , the photodiode PD is coupled between the pixel global reset transistor and the first charge transfer transistor, and the storage node is coupled between the first charge transfer transistor and the second charge transfer transistor.
[0030] The photodiode PD is used to accumulate charges generated by the photoelectric effect, the pixel reset transistor GRST is used to reset the photodiode PD, the first charge transfer transistor TX1 is used to transfer the accumulated charges of the photodiode PD to the storage node MN, and the second charge transfer transistor The transistor TX2 is used for transferring the charge stored in the storage node MN to the floating diffusion node FD, and the reset transistor RST is used for resetting the voltage of the floating diffusion node FD.
[0031] When the transistor gate operates from a low level->high level->low level, the charge collected by the photodiode exposure is transferred to the storage node below the transistor. TX1 is also a switch controlled by the gate voltage. When the gate of the transistor operates from a low level -> a high level -> a low level, the charge at the storage node is transferred to the floating diffusion node FD. RST is a reset transistor. When the gate of the transistor is at a high level, the voltage of the floating diffusion node is reset to a high potential, and the electrons on the floating diffusion node FD are emptied.
[0032] The pixel readout circuit includes a DC blocking capacitor C1, and two ends of the DC blocking capacitor C1 are respectively coupled to the floating diffusion node FD and the CTIA for blocking DC.
[0033] CTIA includes an integrating capacitor C2, an initialization transistor INIT and a source follower SF. One end of the blocking capacitor C1 is coupled to the floating diffusion node FD, and the other end is coupled to the gate of the source follower SF. The source is connected to the reference voltage V ref, the drain stage of the source follower is used as the signal output terminal; the two ends of the integrating capacitor C2 are respectively coupled to the gate and the drain stage of the source follower SF for integrating and amplifying the signal to be output by the source follower SF ; The source and drain of the initialization transistor INIT are respectively coupled to both ends of the integrating capacitor C2 for resetting the integrating capacitor C2.
[0034] When the gate of the initialization transistor INIT is high, both ends of the integrating capacitor C2 are reset to V ref , at this time, the pixel output is sampled to obtain the reset voltage; when the initialization transistor INIT is at a low level, the charge on the floating diffusion node FD is integrated and amplified by the integrating capacitor C2 and then output to the pixel output signal transmission line. At this time, the pixel output voltage is sampled , the signal voltage can be obtained, and correlated double sampling can be used to reduce the 1/f noise and reset noise of the amplifier.
[0035] The integrating capacitor C2 in the CTIA selects a capacitance value according to design requirements or is designed as an optional capacitor, and adjusts the size of the integrating capacitor C2 according to the requirements of pixel conversion gain (CVG for short).
[0036] Since the size of the CVG is related to the DC blocking capacitor C1 and the integrating capacitor C2, the selection of the DC blocking capacitor C1 and the integrating capacitor C2 can enable the image sensor to obtain a larger controllable CVG.
[0037] The source follower SF in CTIA adopts a single-tube common source stage amplifier to reduce the pixel layout area and achieve the purpose of reducing noise. In one example of the present invention, the single-tube common-source stage amplifier adopts low-threshold low-noise type transistors to achieve low noise and large output swing.
[0038] Look back figure 1 , the pixel readout circuit also includes a load current source CS and a programmable gain amplifier (Programmable Gain Amplifier, PGA for short), the number of the load current source CS is the same as that of the sub-pixel unit 1, and the load current source CS is one with the sub-pixel unit 1. Correspondingly, each load current source CS is coupled to the source follower SF in the corresponding sub-pixel unit 1 to provide a bias current for the source follower SF, and at the same time for the parasitic capacitance of the pixel output signal transmission line provide charging current.
[0039] Each sub-pixel unit 1 has its own pixel output signal transmission line, and outputs the voltage signal to the PGA through the respective pixel output signal transmission line. The PGA further amplifies and sums the voltage signals of each channel.
[0040] image 3 The architecture of a pixel array according to one embodiment of the invention is shown.
[0041] like image 3 As shown, the pixel readout circuit further includes a sample/hold circuit ((Sample/Hold, S/H for short) and an A/D converter (Analog-to Digital Converter, ADC for short), S/H is coupled to PGA, A/ The D converter is coupled with the S/H, and the voltage signal added and amplified by the PGA is then sampled and read out by the S/H, and finally converted into a digital signal by the ADC and output to the off-chip for data processing.
[0042] When multiple pixels ( image 3 When forming a pixel array, the sub-pixel units that make up each pixel are equipped with CTIA, and each column of pixels is equipped with PGA, S/H and ADC.
[0043] In the prior art, the design of the column-level CTIA makes the signal line at the input end of the CTIA very long, resulting in a large parasitic capacitance, and thus more noise. Since each sub-pixel unit is configured with a CTIA, the length of the signal line at the input end is shortened, so that the capacitance at the input end of the CTIA is very small, and the output noise of the CTIA is very small.
[0044] The present invention controls and drives the pixels in segments, so that there is no gap in the vertical direction for the photosensitive surface. Compared with the area array image sensor or the line array sensor composed of short diodes, there is a physical gap in space between the photodiodes in the vertical direction. Therefore, for the image sensor of the same height, the image sensor provided by the present invention will obtain a larger size. full well capacity.
[0045] In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.
[0046] Although the embodiments of the present invention have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and should not be construed as limiting the present invention. Embodiments are subject to variations, modifications, substitutions and variations.
[0047] The above specific embodiments of the present invention do not constitute a limitation on the protection scope of the present invention. Any other corresponding changes and modifications made according to the technical concept of the present invention shall be included in the protection scope of the claims of the present invention.
