4results about How to "Increase full well capacity" patented technology

The embodiment of the present application discloses an image sensor and an electronic information device for improving full well capacity. The image sensor comprises: a photodiode formed in a semiconductor substrate; the photodiode comprises at least a first doped layer, a second doped layer and a columnar third doped region; the second doped layer wraps the side and bottom of the third doped region; the first doped layer wraps the side and bottom of the second doped layer; the first doped layer and the second doped layer form a first lateral PN junction; the second doped layer and the third doped region form a second lateral PN junction; wherein the first doped layer and the third doped region have the same conductivity type, and the conductivity type is opposite to that of the second doped layer. The embodiment of the present application replaces the central part of the photodiode with a columnar ion doped region (for example, a P-type layer), so that the image sensor with the epitaxial structure can effectively improve the full well capacity, effectively reduce the depletion potential of the center of the photodiode, avoid the occurrence of lag, and reduce the dark current.

This invention provides a pixel structure and its operating method for a radiation-hardened 4T CMOS image sensor. The pixel structure includes a transmission transistor, a reset transistor, a source follower, a row select transistor, an STI bias gate, a photodiode, a floating node, a shallow trench isolation region, and a P-type substrate. The photodiode is surrounded by a P-type substrate, which is enclosed by the shallow trench isolation region. A portion of the shallow trench isolation region is covered by an STI bias gate. The lower right corner of the photodiode is connected to one side of the transmission transistor, and the other side of the transmission transistor is connected to the floating node. The reset transistor, row select transistor, and source follower are sequentially connected after the floating node. The negative bias V of the STIX designed in this invention... STI negative bias V with TX TX The shutdown voltage effectively improves the radiation resistance of the device by suppressing the generation of interface state trap charges at the STI-pixel interface and the generation of dark current in the TX-PD overlap region under the TID effect.

This invention discloses a method for forming a patterned sensor, comprising: providing a substrate; etching the substrate to form trenches in the substrate; and pre-treating the surface of the trenches before forming an epitaxial doped layer in the trenches to change the ion doping concentration gradient distribution in a portion of the substrate at the trench interface, thereby reducing the mutual compensation caused by the diffusion of doped ions near the PN junction interface of the photodiode in subsequent process steps, thereby improving the full-well capacity of the photodiode.

The application provides an image sensor forming method and an image sensor. The forming process of the image sensor comprises at least two bonding processes of a semiconductor substrate wafer; wherein, a lateral PN junction and a pinning layer are formed in the semiconductor substrate wafer before the first bonding, and a logic circuit region is formed after the first bonding and before the second bonding. The technology in the application has high feasibility because of simple process, high full-well capacity and completion through a self-alignment process, and is not limited by temperature.