Negative capacitance field effect transistor of ferroelectric layers made of different materials and preparation method thereof

Abstract

The invention relates to a negative capacitance field effect transistor of ferroelectric layers made of different materials and a preparation method thereof. The transistor comprises a substrate, a buried oxide layer, a source region formed based on a top layer, a drain region formed based on the top layer, a fully-depleted or partially-depleted channel formed based on the top layer, side walls, a gate oxide layer, a negative capacitance ferroelectric layer and a metal layer, wherein the gate oxide layer, the negative capacitance ferroelectric layer and the metal layer are isolated between the source region and the drain region through the side walls; the transistor is characterized in that the negative capacitance ferroelectric layer is formed by splicing a first ferroelectric layer and a second ferroelectric layer, wherein the first ferroelectric layer and the second ferroelectric layer are made of different ferroelectric materials, so that the negative capacitance ferroelectric layers with different gate materials have a linear amplification effect on gate voltage amplification, and have a better control capability on the gate voltage amplification effect; and meanwhile, the negative capacitance field effect transistor with ferroelectric layers made of different materials has higher saturation region current and lower sub-threshold slope under the same gate voltage, and the sub-threshold slope can be lower than a theoretical limit value 60mV / dec, so that the performance of the transistor is improved.

Description

technical field [0001] The present application relates to the technical field of semiconductor devices, in particular to a negative capacitance field effect transistor with a ferroelectric layer made of different materials and a preparation method thereof. Background technique [0002] The continuous development of Moore's Law has led to the continuous reduction of the feature size of semiconductor devices, the power density of integrated circuits is also increasing, the operating temperature of chips is getting higher and higher, and the reliability and performance are greatly reduced. Reducing the subthreshold swing of transistors is an effective way to reduce the supply voltage and power consumption of integrated circuits. Negative capacitance field effect transistor (Negative capacitance field effect transistor, NCFET), as the latest low-power transistor in recent years, has great potential. Compared with MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET...

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Problems solved by technology

The dual-gate negative capacitance transistor can improve the sub-threshold swing of the transistor, but the improvement effect is not obvious

[0004] Therefore, the current negative capacitance transistor structure is limited in improving the sub-threshold characteristics of the transistor or reducing static power consumption, and cannot linearly control the amplification of the gate voltage, and its performance is low

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