Power supply network simulation method and system based on spectrogram sparsification

Abstract

The invention provides a power supply network simulation method based on spectrogram rarefaction, and the method comprises the steps: building a weighted undirected graph corresponding to an SPICE netlist of a power supply network, a right-end item and a netlist Laplacian matrix corresponding to the weighted undirected graph through the SPICE netlist, and obtaining a sparse subgraph of the weighted undirected graph; establishing a sparse Laplacian matrix corresponding to the sparse subgraph, and removing rows and columns corresponding to the grounding points in the netlist Laplacian matrix and the sparse Laplacian matrix; carrying out Cholesky decomposition on the sparse Laplacian matrix LP to obtain a triangular matrix; setting a convergence threshold, taking the triangular matrix as a precondition sub-to operate a precondition conjugate gradient method to solve a linear equation set LGx = b, obtaining an approximate solution x, i.e., obtaining a simulation result of the power supply network. By the adoption of the scheme, the overall operation time of an iteration solution is accelerated by more than four times while the similarity with an original image is guaranteed, and the time for simulating the power supply network in the chip is greatly shortened.

Description

technical field [0001] The present application relates to a method and system for simulating an on-chip power supply network based on spectrogram sparseness, and belongs to the technical field of physical verification and analysis of integrated circuits. Background technique [0002] In the process of IC backend design, in order to verify the correctness of the design, it is necessary to simulate the circuit. As a kind of circuit simulation, the simulation of power supply network is an important step in the back-end process of integrated circuits. The power supply network is the interconnection network that connects the external power supply to all the transistors on the chip. As the process node enters below 7nm, the number of transistors on the chip becomes more and more, the power supply network becomes more and more complex, and the scale of the matrix that needs to be solved in the simulation of the power supply network becomes larger and larger. Therefore, in the bac...

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Problems solved by technology

However, the solution of Laplacian matrix includes three processes of preconditioner construction, preconditioner matrix decomposition and PCG. GRASS wil...

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