Forming method of semiconductor structure

Abstract

The invention relates to a forming method of a semiconductor structure. The semiconductor structure comprises a semiconductor substrate; an oxide layer on the semiconductor substrate; a high-dielectric-constant gate dielectric layer and a metal gate structure, which are staggered with the stack of the semiconductor layers; and an epitaxial source/drain structure adjacent to the high-dielectric-constant gate dielectric layer and the metal gate structure, wherein the oxide layer defines a bottom of the epitaxial source/drain structure.

Description

technical field [0001] Embodiments of the present invention relate to an isolation structure and its forming method, which are configured to block or eliminate the leakage current generated by the epitaxial source / drain structure in the all-around gate field effect transistor. Background technique [0002] The semiconductor industry has experienced rapid growth. Technological advances in semiconductor materials and design have resulted in each generation of semiconductor devices having smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (eg, the number of interconnect devices per unit chip area) generally increases as geometric dimensions (eg, the smallest component or circuit that can be produced by the fabrication process employed) shrink. A shrinking process is often beneficial for increased throughput and lower associated costs. However, these advances have also increased the complexity of handling...

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Problems solved by technology

In another example, the process of forming source / drain recesses may cause depth variations in the final epitaxial source / drain structures, negatively causing leakage currents

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