Gain Calibration Method of Pipeline ADC Between Stages Based on Comparison Time Detector

Abstract

The invention belongs to the technical field of analog integrated circuits, in particular to a method for calibrating gain between stages of a pipeline ADC based on a comparison time detector. The method of the invention realizes the calibration of the gain error of the amplifier based on comparing the characteristics of the time detector circuit. The comparison time detector is commonly used in the SAR ADC to calibrate the capacitance mismatch at the beginning. The invention uses the comparison time detector in the pipeline ADC, uses the comparison time detector to calibrate the inter-stage gain error of the pipeline ADC, and improves The algorithm solves the problem of calibration accuracy degradation caused by comparator offset. The principle of the inter-stage gain calibration method proposed by the present invention is simple and easy to implement, and can be applied to any pipelined analog-to-digital converter, and is used to calibrate the error caused by the inter-stage gain error in the output codeword of the pipelined analog-to-digital converter, which is significantly The calibration accuracy of the inter-stage gain is greatly improved, thereby effectively improving the performance of the overall ADC.

Description

technical field [0001] The invention belongs to the technical field of analog integrated circuits, in particular to an inter-stage gain calibration method of a pipeline ADC based on a comparison time detector. Background technique [0002] The pipeline ADC combines high speed and high precision, and is widely used in modern electronic equipment such as communication systems, test equipment and phased array radars. The pipeline ADC is formed by cascading conversion sub-stages with the same structure that work under dual-phase non-overlapping clocks. Sub ADC composition. Non-idealities such as charge injection effects of switches, sampling capacitor mismatches, comparator offsets, finite gain of op amps, and nonlinear effects in the sub-stage limit the accuracy that the converter can ultimately achieve. In order to reduce the influence of non-ideal factors and improve the performance of the ADC, it is usually necessary to calibrate the ADC. The calibration process includes ...

AI Technical Summary

Problems solved by technology

The comparison time detector is commonly used in the SAR ADC to calibrate the capacitance mismatch at the beginning. The present invention applies the comparison time detector to the pipeline ADC, uses the comparison time detector to calibrate the inter-stage gain error of the pipeline ADC, and improves The algorithm solves the problem of calibration accuracy degradation caused by comparator offset

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