Level shift circuit suitable for GaN half-bridge gate driving

Abstract

The invention belongs to the technical field of power supplies, and particularly relates to a level shift circuit suitable for GaN half-bridge gate driving. According to the level shift circuit provided by the invention, through the synergistic effect of the active clamping level shift circuit controlled by a PWM signal and the acceleration module controlled by the short pulse, the limitation of a large voltage dynamic range on an LDMOS parasitic capacitor on the speed is effectively avoided, and high-speed level conversion is realized. Meanwhile, nodes with relatively low stray capacitance in the circuit are separated from the output through the decoupling acceleration circuit, logic error overturning caused by charging and discharging of the stray capacitance opposite to the ground is effectively avoided in the dV / dt conversion process, and the dV / dt noise suppression capability is improved.

Description

technical field [0001] The invention belongs to the technical field of power supplies, and in particular relates to a level shift circuit suitable for GaN half-bridge gate driving. Background technique [0002] GaN power devices have smaller on-resistance and parasitic capacitance than Si MOSFET power devices, and have been considered as a good solution for miniaturizing power systems. As the core module in the GaN half-bridge gate drive circuit, the speed of the level shift circuit and the ability to resist the dV / dt interference of the floating power supply rail directly determine the operating frequency and reliability of the GaN half-bridge gate drive circuit. GaN gate drive circuits generally have a switching frequency as high as several MHz to tens of MHz, which makes the transmission delay of the GaN gate drive circuit as low as ten nanoseconds. Due to the extremely low parasitic capacitance of GaN power devices, the switching speed of GaN half-bridge switching nodes...

AI Technical Summary

Problems solved by technology

When the dV / dt of the switching node is high, the IP is large, and the undershoot and overshoot will touch the flipping threshold of the subsequent logic circuit, causing the GaN power tube to be turned on or off by mistake, causing system failure

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