Read voltage optimization method of memory cell, controller of 3D memory and operation method of controller

A memory cell and read voltage technology, which is applied in the field of memory, can solve the problems of increased time delay, threshold voltage distribution shift, and reduced reading speed of 3D memory, so as to achieve the effect of improving reliability and reducing time delay

A memory cell and read voltage technology, which is applied in the field of memory, can solve the problems of increased time delay, threshold voltage distribution shift, and reduced reading speed of 3D memory, so as to achieve the effect of improving reliability and reducing time delay

CN113223593AActive Publication Date: 2021-08-06MAXIO TECH HANGZHOU LTD
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  • Read voltage optimization method of memory cell, controller of 3D memory and operation method of controller
  • Read voltage optimization method of memory cell, controller of 3D memory and operation method of controller
  • Read voltage optimization method of memory cell, controller of 3D memory and operation method of controller

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Embodiment Construction

[0030]Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements or modules are denoted by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale.

[0031] It should be understood that in the following description, "circuitry" may include single or multiple combined hardware circuits, programmable circuits, state machine circuits and / or elements capable of storing instructions for execution by programmable circuits. When an element or circuit is said to be "connected to" another element or is said to be "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements and the connection between elements can be be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directl...

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Abstract

The invention discloses a reading voltage optimization method of a memory cell. The memory cell is selected from a plurality of memory cells corresponding to a selected physical page. The read voltage optimization method comprises the following steps: counting the number of memory cells with a first threshold voltage to obtain a first number; counting the number of the memory cells with the second threshold voltage to obtain a second number; setting an optimal reading voltage based on the first number, the second number and the adjustment parameter, wherein different adjusting parameters are set according to different data storage time, read interference, cross temperature and programming / erasing times. According to the reading voltage optimization method of the memory cell, the controller of the 3D memory and the operation method of the controller, when the optimal reading voltage is set, only the limited number of times of reading is needed, the time delay for determining the optimal reading voltage is effectively reduced, and the adjustment parameters are set based on parameters such as reading interference and programming / erasing times, and the accuracy and reliability of products are improved.

Description

technical field [0001] The invention relates to memory technology, in particular to a method for optimizing the reading voltage of a memory unit, a controller of a 3D memory and an operation method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] The 3D memory device is mainly used as a non-volatile flash memory. The two main non-volatile flash memory technologies use NA...

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Application Information

Patent Timeline
06 Aug 2021
Publication
CN113223593A
IPC
G11C16/26; G11C16/34; G06F11/10
CPC
G11C16/26; G11C16/3404; G06F11/1068; Y02D10/00
Inventors
张旭航; 喻小帆