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Dipole design high-k gate dielectric and method of forming same

A dielectric layer and gate electrode technology, applied in circuits, electrical components, semiconductor devices, etc., can solve problems such as difficult threshold voltage adjustment

Pending Publication Date: 2021-08-13
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the threshold voltage can be changed, it is difficult to tune the threshold voltage to the desired value and further tuning must be achieved by employing different work function metals and adjusting the thickness of the work function metal

Method used

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  • Dipole design high-k gate dielectric and method of forming same
  • Dipole design high-k gate dielectric and method of forming same
  • Dipole design high-k gate dielectric and method of forming same

Examples

Experimental program
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Effect test

example 1

[0064] Example 1 is a method for forming a semiconductor device, comprising: forming a first oxide layer on a first semiconductor region; depositing a first high-k dielectric layer on the first oxide layer, wherein the A first high-k dielectric layer is formed of a first high-k dielectric material; a second high-k dielectric layer is deposited over the first high-k dielectric layer, wherein the second high-k dielectric layer is made of a material different from the first high-k dielectric layer A second high-k dielectric material of a high-k dielectric material is formed; over the first high-k dielectric layer and the second high-k dielectric layer and in contact with the first high-k dielectric layer and the second high-k dielectric layer A first dipole film is deposited in contact with a k dielectric layer, wherein the first dipole film is in contact with a first layer, and the first layer is the first high-k dielectric layer and the second high-k dielectric layer one of the...

example 9

[0072] Example 9 is a semiconductor device comprising: a first oxide layer on a first semiconductor region; a first high-k dielectric layer including a first high-k dielectric material; a second high-k dielectric layer including a a second high-k dielectric material different from the high-k dielectric material, wherein the second high-k dielectric layer overlies and contacts the first high-k dielectric layer; the first dipole dopants in the first high-k dielectric layer and the second high-k dielectric layer, wherein the first peak concentration of the first dipole dopant is in the first high-k dielectric layer At the first top surface or the second top surface of the second high-k dielectric layer; a gate electrode on the second high-k dielectric layer; and a source / drain region on the gate electrode on one side of the

[0073]Example 10 is the device of Example 9, wherein the first dipole dopant comprises lanthanum.

[0074] Example 11 is the device of example 9, wherein ...

example 15

[0078] Example 15 is a semiconductor device comprising: a first transistor comprising: a first portion of a first high-k dielectric layer; a first portion of a second high-k dielectric layer, wherein the second high-k dielectric layer above the first high-k dielectric layer, and wherein the first high-k dielectric layer and the second high-k dielectric layer have different k values; a first dipole dopant, in the A first peak concentration at the interface between the first portion of the first high-k dielectric layer and the first portion of the second high-k dielectric layer; and a second transistor comprising: a second portion of the first high-k dielectric layer a portion; a second portion of the second high-k dielectric layer; and a second dipole dopant having a second peak concentration at a top surface of the second high-k dielectric layer.

[0079] Example 16 is the device of Example 15, wherein the first dipole dopant is the same as the second dipole dopant.

[0080] ...

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Abstract

The invention relates to a dipole design high-K gate dielectric and a method of forming the same. The method includes forming an oxide layer on a first semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, where the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and in contact with a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, an annealing process is performed to drive dipole dopants in the dipole film into the layer, the dipole film is removed, and a gate electrode is formed over the second high-k dielectric layer.

Description

technical field [0001] The present disclosure generally relates to dipole design high-K gate dielectrics and methods of forming the same. Background technique [0002] Metal oxide semiconductor (MOS) devices are the basic building blocks in integrated circuits. Recent developments in MOS devices include the formation of replacement gates, including high-k gate dielectrics and metal gate electrodes over the high-k gate dielectrics. Formation of the replacement gate typically involves depositing a high-k gate dielectric layer, depositing a metal layer over the high-k gate dielectric layer, and then performing chemical mechanical polishing (CMP) to remove the high-k gate dielectric layer and the metal layer. excess. The remainder of the metal layer forms the metal gate. [0003] In conventional formation methods of MOS devices, the threshold voltage of MOS devices can be adjusted by performing a thermal annealing process while conducting ammonia to process the high-k dielect...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L29/06H01L21/02
CPCH01L29/42364H01L29/0603H01L21/022H01L29/513H01L29/517H01L21/823857H01L21/823462H01L21/28185H01L21/28194H01L29/4966H01L21/0228H01L29/518H01L29/66795H01L21/823437H01L21/823431H01L29/511H01L29/516H01L29/785H01L29/66545H01L21/3115H01L27/0886
Inventor 赖德洋彭峻彦杨世海徐志安
Owner TAIWAN SEMICON MFG CO LTD