BMS parallel operation implementation control method and device and power supply
A control method and technology of a control device, applied in the direction of circuit devices, battery circuit devices, circuits, etc., can solve the problem that a single battery cannot precharge the inverter capacitor, etc.
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Embodiment 1
[0026] In some alternative examples, please refer to figure 1 , figure 1 It is a schematic flowchart of an embodiment of a BMS parallel implementation control method in the present application.
[0027] Such as figure 1 As shown, the first aspect of the present application provides a BMS parallel implementation control method, including:
[0028] S1100. The host sends a preset synchronous calibration command to the slave, wherein the host communicates with at least one slave;
[0029] During implementation, at least two batteries or at least two battery packs are paralleled to form a battery system, each battery or each battery pack includes its corresponding battery management system BMS and pre-charging circuit, that is, multiple BMS boards work together to realize BMS Parallel, when multiple BMSs are working in parallel, first all pre-charging circuits are not turned on. During implementation, the host is provided with a processor, and the BMS parallel implementation co...
Embodiment 2
[0040] In some alternative embodiments, see figure 2 , figure 2 It is a schematic flow chart of another embodiment of the present application.
[0041] Such as figure 2 As shown, when step S1300 is executed and it is determined that there is a deviation in the system clock information, step S1500 is executed.
[0042] S1500. Determine the target slave with deviation;
[0043] S1600. The master sends a synchronous calibration command to the target slave for time verification, and receives system clock information fed back by the target slave after time verification.
[0044]When the master checks the deviation of the system clock information sent back by each slave, it determines the target slave where the deviation occurs. During implementation, when each slave feeds back the system clock information, it also includes the identification information of each slave. The identification information is The unique identification information of the slave, such as the unique IP ...
Embodiment 3
[0046] In some alternative embodiments, see image 3 , image 3 It is a schematic flow chart of system error reporting in an embodiment of the present application.
[0047] Such as image 3 As shown, after step S1600, the BMS parallel implementation control method provided by the present application further includes the following steps:
[0048] S1700. Record the verification information of the time verification performed by the target slave;
[0049] S1800, judging whether the verification information satisfies a preset error reporting condition;
[0050] In order to avoid infinite loops to check the time of the target slave with deviation, the system will record the calibration information of each target slave. During implementation, the calibration information includes the number of calibrations and the calibration time, and the error conditions are pre-stored in the processing In the device, in some embodiments, for example, if the number of verification times reaches ...
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