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Data processing system based on memory intensive algorithm and computer equipment
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A data processing system, memory-intensive technology, used in general-purpose stored-program computers, combinations of various digital computers, architectures with multiple processing units, etc.
Active Publication Date: 2021-08-20
ZHEJIANG NANOMICRO TECH CO LTD +1
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Therefore, how to solve the performance bottleneck of memory read bandwidth is an urgent need for this algorithm.
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Embodiment 1
[0034] In this example, if figure 1 As shown, a memory-intensive algorithm-based data processing system 200 is provided, which includes: a processor 201, a data exchange module, a conversion module 209 and a memory module 213;
[0035] The processor 201 includes a plurality of computing cores, each of which has a plurality of connection interfaces; the data exchange module includes a plurality of switching units, each of which has a plurality of input ports and a plurality of output ports The conversion module 209 includes a plurality of conversion units, each of which has a plurality of conversion input ports and a plurality of conversion output ports; the memory module 213 includes a plurality of memory units;
[0036] Each computing core forms a system block with a switching unit, a conversion unit, and a memory unit, and each connection interface of each computing core is connected to each switching unit of the same system block. The input port is connected, the output po...
Embodiment 2
[0064] In this example, if figure 1 As shown, in the figure, 201 is a processor, 203 is a first-level switch, 205 is a second-level switch, 207 is a third-level switch, 209 is a converter, 211 is a memory control module, and 213 is a memory module.
[0065]Wherein, the processor includes n computing cores, and the computing units in each computing core are 2m. In the present embodiment, the computing cores include Core0, Core1, Core2, Core3, Core4, Core5, and the number of computing cores is 6, each The number of computing units in one computing core is 8, therefore, n=6, m=4. In this embodiment, the system is divided into 6 system blocks according to the number of computing cores, that is, 6 Blocks, including Block1, Block2, Block3, Block4, Block5, and Block6.
[0066] The 2m computing units of each computing core are respectively connected to an input port of a level-1 switch through a connection interface.
[0067] The first-level switch is an m*n crossbar switch, that is...
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Abstract
The invention provides a data processingsystem based on a memory intensive algorithm and computer equipment. The system comprises a processor, a data exchange module, a conversion module and a memory module; the processor comprises a plurality of computing cores; the data exchange module comprises a plurality of exchange units; the conversion module comprises a plurality of conversion units; the memory module comprises a plurality of memory units; each computing core, a switching unit, a conversion unit and a memory unit form a system block, each computing core is connected with the switching unit of the same system block, the switching unit is connected with the conversion unit of the same system block, and each computing core is also connected with the switching units of other system blocks; and each conversion unit is connected with the memory unit of the same system block. The computing cores are connected with the memory units of the different system blocks through the switching module, so that the computing cores read the data of the memory units, and the performance bottleneck caused by the memory bandwidth is avoided.
Description
technical field [0001] The invention relates to the technical field of memory-intensive algorithms, in particular to a data processing system and computer equipment based on memory-intensive algorithms. Background technique [0002] The essence of POW (Proof of Work) is to solve a mathematically difficult problem based on computing power. The key point of solving the problem is that there is no way to find the nonce value we need except for violent enumeration, but for the verification output The result is very simple and easy. [0003] For memory-hard function algorithms, during the operation process, the algorithm needs to repeatedly extract a large amount of data randomly from the memory for operation. The performance bottleneck of this algorithm is memory bandwidth, which prevents multi-core parallel processing from being fully utilized. , so that performance is only related to memory size. [0004] Due to the nature of the Memory-hard algorithm, memory read bandwidth ...
Claims
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