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Re-wiring layer structure and preparation method thereof, and packaging structure and preparation method thereof

A technology of rewiring layer and packaging structure, applied in the field of semiconductor packaging, can solve problems such as complex process

Active Publication Date: 2021-08-31
ZHEJIANG NANOMICRO TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of the above problems, the present application provides a redistribution layer structure and its preparation method, a packaging structure and its preparation method, which solves the technical problem of complex process caused by the separation of the existing RDL interposer and power board

Method used

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  • Re-wiring layer structure and preparation method thereof, and packaging structure and preparation method thereof
  • Re-wiring layer structure and preparation method thereof, and packaging structure and preparation method thereof
  • Re-wiring layer structure and preparation method thereof, and packaging structure and preparation method thereof

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Effect test

Embodiment 1

[0087] see figure 1 , this embodiment provides a redistribution layer structure 10, which is arranged between two adjacent chips, the redistribution layer structure 10 includes: a first insulating layer 101, a plurality of first connectors 102, a plurality of second The connecting piece 103 , the multiple third connecting pieces 104 , the multiple fourth connecting pieces 105 , the second insulating layer 106 , the fifth connecting piece 107 and the bypass capacitor 108 .

[0088] The first insulating layer 101 includes a first sub-insulating layer 1011 , and a second sub-insulating layer 1012 and a third sub-insulating layer 1013 arranged side by side with the first sub-insulating layer 1011 .

[0089] Wherein, the second sub-insulation layer 1012 and the third sub-insulation layer 1013 may be respectively located on two sides of the first sub-insulation layer 1011 .

[0090] The material of the first sub-insulation layer 1011 includes silicon insulation materials, including...

Embodiment 2

[0107] see image 3 with 4 , the present embodiment provides a packaging structure, including: a redistribution layer structure 10, a first micro-bump 12, a second micro-bump 14, a first chip 13, a second chip 15, a first packaging layer 16, a sixth Connector 17 , seventh connector 18 , third micro-bump 19 , fourth micro-bump 20 , package substrate 21 and second package layer 22 .

[0108] It should be noted that, in order to image 3 The shapes and positions of the redistribution layer structure 10, the first chip 13, the second chip 15 and the packaging substrate 21 are clearly shown in the figure, so image 3 The first micro-bump 12, the second micro-bump 14, the first encapsulation layer 16, the sixth connector 17, the seventh connector 18, the third micro-bump 19, and the fourth micro-bump 20 are not shown in and the second encapsulation layer 22 . but combine Figure 4 It can be understood that the first micro-bump 12, the second micro-bump 14, the first encapsulati...

Embodiment 3

[0130] On the basis of the first embodiment, this embodiment provides a method for preparing the redistribution layer structure 10 .

[0131] Figure 5 It is a schematic flowchart of a method for preparing the redistribution layer structure 10 shown in the embodiment of the present application.

[0132] Such as Figure 5 As shown, the preparation method of the redistribution layer structure 10 of this embodiment includes the following steps:

[0133] Step S110 : providing a temporary substrate 23 .

[0134] Wherein, the material of the temporary substrate 23 may be glass or silicon.

[0135]Step S120 : forming a third insulating layer 24 on the temporary substrate 23 .

[0136] Wherein, the material of the third insulating layer 24 is an adhesive material, which can be used to remove the temporary substrate 23 later.

[0137] Step S130 : forming the first insulating layer 101 on the third insulating layer 24 .

[0138] The first insulating layer 101 includes a first sub-...

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Abstract

The invention provides a re-wiring layer structure and a preparation method thereof, and a packaging structure and a preparation method thereof. The re-wiring layer structure is arranged between two adjacent chips, and the re-wiring layer structure comprises a signal connector (a first connector) used for realizing signal connection between the chips, and power supply connecting pieces (a second connecting piece, a third connecting piece and a fourth connecting piece) used for realizing power supply connection between the chips and an external power supply. The power supply connecting pieces are arranged in the same rewiring layer structure (arranged in the same intermediate layer), so that an existing structure in which a power supply board is separated from the intermediate layer is replaced. The structures are simple, the distance between the signal connecting piece and the substrate and the distance between the power connecting piece and the substrate are consistent, the connecting structure is simple, the process precision requirement is low, the process is simple, and the yield is greatly improved.

Description

technical field [0001] The present application relates to the technical field of semiconductor packaging, in particular to a rewiring layer structure and a preparation method thereof, a packaging structure and a preparation method thereof. Background technique [0002] In the past few decades, as predicted by Moore's Law, with the advancement of related technologies such as manufacturing and packaging processes, the number of transistors that can be accommodated on a single chip has indeed been doubling. However, as the semiconductor manufacturing process is getting closer and closer to the physical limit of silicon materials, advanced manufacturing processes below 7nm can no longer bring about cost reductions. On the contrary, the reduction in area has brought about a huge increase in design and manufacturing costs. Moore's Law can no longer maintain the original There is a performance-to-price ratio. Therefore, the introduction of advanced packaging technology in the indu...

Claims

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Application Information

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IPC IPC(8): H01L23/538H01L23/498H01L25/18H01L21/48H01L21/98
CPCH01L23/5386H01L23/5384H01L23/49838H01L23/49827H01L25/18H01L21/4846H01L25/50
Inventor 胡楠孔剑平王琪崔传荣
Owner ZHEJIANG NANOMICRO TECH CO LTD
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