Automatic testbench generation method
An automatic generation and variable technology, which is applied in the fields of instrumentation, calculation, electrical and digital data processing, etc., can solve the problems of time-consuming, complicated data generation and analysis principles and processes, and achieve automatic generation and avoid the long cycle of the test platform. Effect
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[0078] The present invention provides a testbench automatic generation method, the overall structure of the method is as follows figure 1 shown, including the following steps:
[0079] Step 1. Obtain the basic information provided by the user, such as figure 2 Shown: the name of the designer provided by the user is Iron_Man, the expected simulation tool is NC_verilog, and the file name for storing the top-level module is not specified; therefore author=Iron_Man, sim_tool=NC_verilog, filename_top_module is empty;
[0080] Step 2. Check and create a new folder;
[0081] Step 3, obtaining the module name of the top-level module and the file name of the storage top-level module;
[0082] Step 4, obtain the IO port of the top module;
[0083] Step 5, generate testbench main file;
[0084] Step 6. Generate a separate testcase template;
[0085] Step 7, configure the simulation environment;
[0086] Step 8. Print the running process log file, including the top-level file path,...
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