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Automatic testbench generation method

An automatic generation and variable technology, which is applied in the fields of instrumentation, calculation, electrical and digital data processing, etc., can solve the problems of time-consuming, complicated data generation and analysis principles and processes, and achieve automatic generation and avoid the long cycle of the test platform. Effect

Active Publication Date: 2021-09-03
58TH RES INST OF CETC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] For large-scale integrated circuits, there may be dozens to hundreds of interfaces, and it will take a lot of time to build and debug the testbench test platform
In addition, the principles and processes of data generation and analysis are very cumbersome, because it involves communication principles such as sampling theorem, and requires a certain MATLAB programming foundation

Method used

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Embodiment 1

[0078] The present invention provides a testbench automatic generation method, the overall structure of the method is as follows figure 1 shown, including the following steps:

[0079] Step 1. Obtain the basic information provided by the user, such as figure 2 Shown: the name of the designer provided by the user is Iron_Man, the expected simulation tool is NC_verilog, and the file name for storing the top-level module is not specified; therefore author=Iron_Man, sim_tool=NC_verilog, filename_top_module is empty;

[0080] Step 2. Check and create a new folder;

[0081] Step 3, obtaining the module name of the top-level module and the file name of the storage top-level module;

[0082] Step 4, obtain the IO port of the top module;

[0083] Step 5, generate testbench main file;

[0084] Step 6. Generate a separate testcase template;

[0085] Step 7, configure the simulation environment;

[0086] Step 8. Print the running process log file, including the top-level file path,...

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Abstract

The invention discloses an automatic testbench generation method, and belongs to the field of digital integrated circuits. The method includes obtaining basic information provided by a user, wherein the basic information comprises a designer name, a simulation tool expected to be adopted and a file name for storing a top layer module; checking and creating a new folder; obtaining a module name of the top-layer module and a file name for storing the top-layer module; obtaining an IO port of the top layer module; forming a testbench main body file; forming an independent testcase template; configuring a simulation environment; and printing a running process log file, wherein the running process log file comprises a top-layer file path, a top-layer model name, a simulation tool type and a path for automatically generating tb. According to the invention, a complete testbench can be generated, and a user only needs to modify the testcase according to requirements on the basis of the testbench, so that a simulation test can be carried out; the problems of long period and high difficulty in building and debugging a testbench test platform are avoided; and the automatic generation of the testbench in the development process is realized.

Description

technical field [0001] The invention relates to the technical field of digital integrated circuits, in particular to a testbench automatic generation method. Background technique [0002] In the design process of digital integrated circuits, for the designed RTL code or the synthesized gate-level netlist, it is usually necessary to design a dedicated testbench to simulate whether the function or timing of the model meets the design requirements. The content of testbench includes: defining the interface type according to the model to be tested, initializing the input interface signal, instantiating the model, saving the waveform, importing and saving the data, etc. For a model with an SPI interface, it is necessary to write a task to implement the spi read and write function. For the data processing unit, it is necessary to generate data text, and the exported data needs to be analyzed by spectrum. [0003] For large-scale integrated circuits, there may be dozens to hundreds...

Claims

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Application Information

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IPC IPC(8): G06F30/367G06F30/327
CPCG06F30/367G06F30/327
Inventor 邵杰蒋颖丹万书芹苏小波
Owner 58TH RES INST OF CETC