Wafer-level fan-out packaging method and structure with high heat dissipation performance
A packaging method and packaging structure technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of small bonding area between chips and packaging materials, low strength of packaging structure, and fragility
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[0029] The present invention provides a wafer-level fan-out packaging method with high heat dissipation performance, comprising the following steps:
[0030] Such as figure 1 As shown, a functional chip 13 is provided, and a heat sink 11 is mounted in the center of the back; the heat sink 11 is mounted on the back of the functional chip 13 and centered by thermally conductive adhesive or metal solder; wherein the thermally conductive adhesive or metal used Solder has the characteristics of firm connection, good thermal conductivity, and high temperature resistance. Its firm connection ensures that there will be no problems such as cracking, displacement, and delamination between the functional chip 13 and the heat sink 11 in various process environments. The feature of good performance ensures the rapid transfer of heat from the functional chip 13 to the heat sink 11, and its high temperature resistance feature ensures the stability and reliability of the bonding surface in ot...
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