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Wafer-level fan-out packaging method and structure with high heat dissipation performance

A packaging method and packaging structure technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of small bonding area between chips and packaging materials, low strength of packaging structure, and fragility

Inactive Publication Date: 2021-09-10
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the heat dissipation problem is ignored, there will be serious consequences of interface circuit connection mismatch and even the overall circuit failure; if the thickness of the packaging material is forcibly thinned to achieve the purpose of heat dissipation, there will be too small bonding area between the chip and the packaging material, resulting in too much structural strength of the package. low risk of breakage

Method used

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  • Wafer-level fan-out packaging method and structure with high heat dissipation performance
  • Wafer-level fan-out packaging method and structure with high heat dissipation performance
  • Wafer-level fan-out packaging method and structure with high heat dissipation performance

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Embodiment 1

[0029] The present invention provides a wafer-level fan-out packaging method with high heat dissipation performance, comprising the following steps:

[0030] Such as figure 1 As shown, a functional chip 13 is provided, and a heat sink 11 is mounted in the center of the back; the heat sink 11 is mounted on the back of the functional chip 13 and centered by thermally conductive adhesive or metal solder; wherein the thermally conductive adhesive or metal used Solder has the characteristics of firm connection, good thermal conductivity, and high temperature resistance. Its firm connection ensures that there will be no problems such as cracking, displacement, and delamination between the functional chip 13 and the heat sink 11 in various process environments. The feature of good performance ensures the rapid transfer of heat from the functional chip 13 to the heat sink 11, and its high temperature resistance feature ensures the stability and reliability of the bonding surface in ot...

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Abstract

The invention discloses a wafer-level fan-out packaging method and structure with high heat dissipation performance, and belongs to the field of wafer-level packaging. The method comprises the following steps of: providing a functional chip, and mounting a radiating fin in the middle of the back surface of the functional chip; packaging the functional chip and the radiating fin by using a packaging material; manufacturing a metal connecting line and a dielectric layer on the front surface of the functional chip; and grinding the packaging material until the radiating fin is exposed, manufacturing a leading-out pin, and performing cutting to obtain a single circuit, thereby forming a complete wafer-level packaging body. The wafer-level fan-out packaging structure with the high heat dissipation performance is suitable for wafer-level fan-out packaging, the overall structural strength of the packaging body can be guaranteed, and the requirement that part of the back face of part of the chip need to be grounded can be met; the heat dissipation performance of the functional chip in the wafer-level packaging is effectively improved, and the problem that the heat dissipation performance of a chip in traditional wafer-level packaging is poor is effectively solved.

Description

technical field [0001] The invention relates to the technical field of wafer-level packaging, in particular to a wafer-level fan-out packaging method and structure with high heat dissipation performance. Background technique [0002] With the rapid progress of modern science and technology and the rapid growth of military and civilian market demand, the dimensions of various electronic products are getting smaller and smaller, and the demand for various electronic components is also increasing year by year. The inherent advantages of mass production are more widely used, but the problem of difficult heat dissipation of its chips is also becoming more and more prominent. If the heat dissipation problem is ignored, there will be serious consequences of interface circuit connection mismatch and even the overall circuit failure; if the thickness of the packaging material is forcibly thinned to achieve the purpose of heat dissipation, the bonding area between the chip and the pac...

Claims

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Application Information

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IPC IPC(8): H01L21/48H01L21/56H01L23/367H01L23/498H01L23/31
CPCH01L21/4846H01L21/4853H01L21/56H01L23/3672H01L23/49811H01L23/3185
Inventor 王波葛迎飞张荣臻
Owner 58TH RES INST OF CETC