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Chip packaging structure and manufacturing method thereof

A chip packaging structure and chip technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problems of impact, time-consuming, and quantity consumption.

Active Publication Date: 2021-09-10
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in this process route, the metal Faraday cage is completed before plastic packaging, which will affect the front end of line (FEOL)
Moreover, the metal Faraday cage needs to consume a huge number of conductive elements, and the cost is high
In addition, the process is limited by the capabilities of the wire bonder (WB) machine, the length of the conductive elements that can be used
Parameters such as density are limited and time-consuming

Method used

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  • Chip packaging structure and manufacturing method thereof
  • Chip packaging structure and manufacturing method thereof
  • Chip packaging structure and manufacturing method thereof

Examples

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Embodiment Construction

[0043]For a better understanding of the application, various aspects of the application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are descriptions of exemplary embodiments of the application only, and are not intended to limit the scope of the application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It should be noted that in this specification, expressions of first, second, third, etc. are only used to distinguish one feature from another, and do not represent any limitation on the features. Therefore, the second vertical conductive lines discussed below may also be referred to as first vertical conductive lines without departing from the teachings of the present application. vice versa.

[0045] In the drawings, the ...

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Abstract

The invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises: a packaging body, wherein at least one chip, a grounding bonding pad and a conductive element are packaged in the packaging body, the grounding bonding pad and the conductive element are electrically connected with each other, the packaging body is provided with a first surface and a second surface which are opposite along a first direction, and a first peripheral surface which is connected with the first surface and the second surface, and one surface of the grounding bonding pad is exposed to the first surface, a redistribution layer disposed on the second surface of the packaging body and including a ground wire electrically connected to the conductive element, and a shielding layer covering the first surface, the first circumferential surface, and a side surface of the redistribution layer, and electrically connected to the exposed surface of the grounding bonding pad.

Description

technical field [0001] The present application relates to the field of semiconductors, and more specifically, to a chip packaging structure and a manufacturing method. Background technique [0002] If the working circuit composed of semiconductors is subjected to external electromagnetic interference (Electromagnetic Interference, EMI) during operation, the operating performance may be affected. Even when the interference is strong, some sensitive chip packaging structures are at risk of damage. In addition to various external interference sources, in high-speed PCB and system design, high-frequency signal lines, integrated circuit pins, and various connectors may also become radiation interference sources with antenna characteristics. It can emit electromagnetic waves and affect the normal operation of various devices in the system, including the chip packaging structure. [0003] Anti-electromagnetic interference is a hot topic in the semiconductor industry, especially i...

Claims

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Application Information

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IPC IPC(8): H01L23/528H01L23/485H01L23/552H01L21/56H01L21/60
CPCH01L23/5286H01L23/552H01L23/4824H01L23/485H01L24/03H01L21/568H01L24/85H01L2224/0231H01L2224/02331H01L2224/02333H01L2224/02381
Inventor 曾心如陈鹏徐震黄小强周厚德
Owner YANGTZE MEMORY TECH CO LTD
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