An output drive circuit with self-adaptive output drive capability

Abstract

The invention discloses an output drive circuit with self-adaptive output drive capability, comprising a first inverter, a second inverter, a third inverter, a fourth inverter, a reference capacitor Cref, a NAND gate, or A NOT gate, a PMOS transistor and an NMOS transistor; one input terminal of the NAND gate is connected to the input signal IN after passing through the first inverter and the third inverter, and the other input terminal of the NAND gate passes through the second inverter. The inverter is connected to the input signal IN; one input terminal of the NOR gate is connected to the input signal IN after passing through the second inverter and the fourth inverter, and the other input terminal of the NAND gate passes through the first The inverter is connected to the input signal IN; an output terminal of the second inverter is connected to the reference capacitor Cref; the output port of the NAND gate is connected to the gate of the PMOS transistor; the output terminal of the NOR gate is connected to the NMOS gate of the transistor. The invention can dynamically adjust the output driving capability in real time according to the change of the external load capacitance, and greatly reduce the change of the rise and fall time of the output signal.

Description

technical field [0001] The invention relates to the technical field of integrated circuit output drive circuits, in particular to an output drive circuit with self-adaptive output drive capability. Background technique [0002] Such as figure 1 As shown, the output driving circuit of the integrated circuit can be equivalent to an inverter with a small on-resistance of the transistor, which is used to provide a large driving current for the external load capacitor CL. However, the driving current of the traditional integrated circuit output driving circuit is generally fixed when the integrated circuit is designed. If the external load capacitance is too large, the rise and fall time of the output signal will increase, and the maximum data transfer rate that the output signal can achieve will decrease; if the external load capacitance is too small, the rise and fall time of the output signal will decrease, and the signal-to-signal Crosstalk will increase and even lead to sy...

AI Technical Summary

Problems solved by technology

However, this solution not only increases the complexity of the external circuit design, but also has high cost and low efficiency.

[0004] It can be seen from the above that since the output driving current of the existing traditional integrated circuit cannot be dynamically adjusted, and the change of the external load capacitance will affect the rise and fall time of the output signal, which will eventually lead to problems such as a decrease in the maximum data transmission rate or electromagnetic interference. thereby greatly degrading the performance of the drive circuit

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