Wafer assembly
A technology of wafers and components, applied in the direction of electrical components, electrical solid devices, semiconductor devices, etc., can solve problems affecting the efficiency and accuracy of wafer bonding recognition, small pattern size, etc., to improve recognition efficiency and accuracy, improve key Combined precision, the effect of large chip effective area
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[0033] As described in the background, as the 3D-IC design cutting channel width is getting smaller, it is necessary to leave the pattern size of the alignment marker, which affects the crystal bonding recognition efficiency and accuracy. Specifically, such as figure 1 As shown, the wafer assembly includes two wafers, including alignment markers 01, and other wafers include alignment mark 02, alignment mark 01 matches alignment mark 02 for two wafers allow. The line width of the alignment mark 01 is b, and the line width of the alignment mark 02 is a, and the line length of the alignment mark 02 is c. The cutting channel S width D is increasing, and the line width A of the alignment mark 02 is added to the line width B of the alignment mark 01, and the line length of the alignment mark 02 is smaller than the cutting channel width D, that is, A + B + C
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