Power supply voltage stabilizing chip for improving power supply rejection ratio

Abstract

The invention relates to an LDO (Low Dropout Regulator) circuit, in particular to a power supply voltage stabilizing chip for improving the power supply rejection ratio. According to the technical scheme, the power supply voltage stabilizing chip capable of improving the power supply rejection ratio comprises an LDO circuit body and further comprises a power supply rejection ratio enhancing circuit connected with the LDO circuit body in a matched mode, and a power supply end of the power supply rejection ratio enhancing circuit is connected with a power supply voltage VDD. The power supply rejection ratio enhancing circuit can generate and output an internal voltage VPP which has an inhibiting effect on power supply voltage VDD, and the internal voltage VPP generated by the power supply rejection ratio enhancing circuit can provide a working voltage needed by the LDO circuit body. The power supply rejection ratio of the LDO circuit can be improved, and the stability and reliability of the performance of the LDO circuit are ensured.

Description

technical field [0001] The invention relates to an LDO circuit, in particular to a power supply voltage stabilizing chip for improving the power supply rejection ratio. Background technique [0002] like figure 1 As shown, it is the circuit schematic diagram of the existing LDO (low dropout regulator) circuit, in which U1 is the main operational amplifier, U2 is the reference voltage source, P1 is the PMOS transistor, and the main operational amplifier U1 loads the gate terminal of the PMOS transistor P1 For the control signal, the resistor R1 and the resistor R2 form a voltage divider network. [0003] During specific work, the main operational amplifier U1, the reference voltage source U2 and the PMOS transistor P are all provided directly by the VDD of the chip. Through actual testing, it is found that the ripple interference of the power supply terminal VDD will be applied to the chip through the main operational amplifier U1 and the reference voltage source U2. The mo...

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Problems solved by technology

[0003] During specific work, the main operational amplifier U1, the reference voltage source U2 and the PMOS transistor P are all provided directly by the VDD of the chip. Through actual testing, it is found that the ripple interference of the power supply terminal VDD will act on the power supply through the main operational amplifier U1 and the reference voltage source U2. The output terminal of the entire LDO circuit, the main operational amplifier U1 and the reference voltage source U2 are directly affected by the VDD ripple, the worse the output PSRR (power supply rejection ratio) index performance will be

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