Bit line leading-out structure and preparation method thereof

Abstract

The invention relates to a bit line leading-out structure and a preparation method thereof. A bit line extending in the Y-axis direction is formed on a substrate; a contact hole covering the bit line in the X-axis direction is formed, and the X-axis direction is perpendicular to the Y-axis direction; and a metal wire covering the contact hole is formed, wherein the contact hole is positioned between the bit line and the metal wire and is contacted with the bit line and the metal wire separately, and the contact area between the contact hole and the metal wire is larger than the contact area between the contact hole and the bit line. According to the bit line leading-out structure, the contact area of the contact hole and the metal line is larger than the contact area of the contact hole and the bit line, so that the contact resistance of the bit line leading-out structure can be reduced.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a bit line lead-out structure and a preparation method of the bit line lead-out structure. Background technique [0002] Semiconductor memory uses transistor arrays to control the charge and discharge of storage capacitors to access data. Wherein, the drain region of the transistor is electrically connected to the bit line. After the bit line is formed on the substrate, a bit line lead-out structure needs to be formed above the bit line, and the bit line is electrically connected to an external control circuit through the bit line lead-out structure. [0003] However, with the continuous improvement of the integration of semiconductor devices, the continuous reduction of the size of the bit line and the continuous reduction of the spacing between the bit lines, the area of ​​the bit line lead-out structure will also be reduced accordingly, so that the distance between the bit line l...

AI Technical Summary

Problems solved by technology

[0003] However, with the continuous improvement of the integration of semiconductor devices, the continuous reduction of the size of the bit line and the continuous reduction of the spacing between the bit lines, the area of ​​the bit line lead-out structure will also be reduced accordingly, so that the distance between the bit line lead-out structure and the corresponding bit line The contact resistance becomes larger, causing the current flowing through the bit line to be too small, thereby reducing the sensing margin of the semiconductor memory and the charging and discharging speed of the storage capacitor

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