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Displacement control circuit and control method

A technology of offset control and circuit, which is applied in recording/reproducing/deleting methods, recording/reproducing with optical methods, magnetic recording, etc., and can solve problems such as difficult offset compensation and difficult realization

Inactive Publication Date: 2004-02-11
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] In the prior art described above, in order to detect the correct amount of amplitude error, it is necessary to use a training signal whose magnetization inversion width is known, and it is difficult to compensate the offset for a reproduced signal without a training signal.
In particular, it is more difficult to implement in the case where the playback signal has the characteristics of an integral system like optical playback
[0015] Even if this existing technology can be used in the recording data signal area, if the sampling rate of the A / D converter is not a multiple of the bit rate, there will be a problem of accuracy

Method used

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  • Displacement control circuit and control method
  • Displacement control circuit and control method
  • Displacement control circuit and control method

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Embodiment 1

[0036] Refer below Figure 1 ~ Figure 3 Embodiment 1 corresponding to the offset control circuit of claim 1 of the present invention and the offset control method of claim 4 of the present invention will be described.

[0037] figure 1 is a diagram showing an offset control circuit according to Embodiment 1 of the present invention.

[0038] For example, when the playback signal has the characteristics of an integral system like an optical disc device, in particular, as in the 8-16 modulation symbol in DVD-ROM (Read Only Memory), 1 or 0 as continuous digital data The recording data area limited to 3T (T is the minimum recording unit) to 11T exists continuously, and the case where the training area and the area where a single pattern called a guide pattern repeats is composed of non-existing symbols is considered as an example. .

[0039] Among them, 8-16 modulation is characterized in that 1 and 0 are modulated so that the probabilities of existence of 1 and 0 as recorded ...

Embodiment 2

[0065] Refer below Figure 4 Now, the offset control circuit in claim 2 of the present invention and the offset control circuit in Embodiment 2 corresponding to the offset control method in claim 5 of the present invention will be described.

[0066] The offset control circuit of the second embodiment has a level for detecting the amount of variation in the DC level of the reproduced signal over time in the control mode of the reference level of the A / D converter 2 described in the first embodiment. A fluctuation detector, in the above-mentioned level fluctuation detector, when it is judged that the amount of fluctuation is small, the reference level of the analog / digital converter 2 is controlled on the basis of the output signal of the first integrator 5, and when it is judged that the amount of fluctuation is When it is larger, the reference level of the A / D converter 2 is controlled based on the output signal of the second integrator 7 .

[0067] Wherein, the above-mentio...

Embodiment 3

[0071] Refer below Figure 5 Next, the offset control circuit in claim 3 of the present invention and the offset control circuit in Embodiment 3 corresponding to the offset control method in claim 6 of the present invention will be described.

[0072] The offset control circuit of this embodiment 3 is that the reference level control circuit 10 described in the above embodiment 1 has Figure 5 composition shown.

[0073]That is, the reference level control circuit 10 includes: using the output signals of the first integrator 5 and the second integrator 7 as input signals, amplifiers 20 and 21 for adjusting the amplification ratio of each signal; loop filter 22 ; adding means 23 for adding the output signal of the amplifier 21 and the output signal of the loop filter 22 .

[0074] The offset control circuit is provided to control the reference level of the A / D converter 2 on the basis of the output of the reference level control circuit 10, so that it can properly control the...

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Abstract

When a playback signal of recorded data which is a DC free code has non-linearity, the playback signal is equalized by a waveform equalization unit, and sampled by an analog-to-digital converter. The sample data is binarized, and an offset amount is detected by utilizing the feature of the DC free code, and then the reference level of the analog-to-digital converter is controlled so that the output of a first integrator becomes 0. Thereafter, the output of a level shift circuit is input to a second integrator, and the level shift amount is controlled so that the output becomes 0. The converged value is retained. After this learning, by using the retained level shift amount, the reference level is controlled so that the output of the second integrator becomes 0, thereby performing speedy and accurate DC offset control.

Description

technical field [0001] The present invention relates to an offset control circuit and an offset control method, in particular to high-speed and accurate direct current for the playback signal of digital data recorded in an optical disc medium, a magneto-optical disc medium, and a magnetic medium. An offset control circuit and an offset control method for flat control. Background technique [0002] A magnetic disk device is one type of devices for recording and reproducing digital data. In magnetic disk devices, with the increase in recording density in recent years, MR heads (Magneto-Resistive Heads) have been introduced as playback heads. [0003] The MR head uses the characteristic that the resistivity p of the MR device changes with the input magnetic field H from the magnetic recording medium to read the recorded information. [0004] In MR devices, it is ideal to use the linear region of the operating curve. Therefore, when the input signal, that is, the recorded mag...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11B5/00G11B5/02G11B5/035G11B7/005G11B11/105G11B20/10
CPCG11B20/10009G11B5/035G11B5/02G11B7/005G11B11/10515G11B2005/0016G11B23/0321B65D25/10
Inventor 小仓洋一丸川昭二
Owner PANASONIC CORP
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