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Positive and negative voltage charge pump single-stage circuits and four-phase charge pump circuit

A four-phase charge pump, charge pump technology, applied in electrical components, conversion equipment without intermediate conversion to AC, output power conversion devices, etc., can solve the problem of high withstand voltage performance of the second PMOS tube PM2, and achieve withstand voltage Low requirements, reduced area, and guaranteed voltage conversion effect

Pending Publication Date: 2021-12-31
PUYA SEMICON SHANGHAI CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This solution requires the second PMOS transistor PM2 to have high withstand voltage performance (close to twice the high-voltage input and output voltage VDD of the charge pump circuit), and it is necessary to add an auxiliary stage

Method used

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  • Positive and negative voltage charge pump single-stage circuits and four-phase charge pump circuit
  • Positive and negative voltage charge pump single-stage circuits and four-phase charge pump circuit
  • Positive and negative voltage charge pump single-stage circuits and four-phase charge pump circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0047] like image 3 As shown, the positive voltage charge pump single-stage circuit includes the zeroth PMOS transistor P0, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the first capacitor C1 and the second capacitor C2;

[0048] The drain terminal of the zeroth PMOS transistor P0 and the gate terminal of the first PMOS transistor P1 are short-circuited as the voltage input terminal IN;

[0049] The gate end and the drain end of the third PMOS transistor P3 are short-circuited with the source end of the second PMOS transistor P2;

[0050] The source terminals of the zeroth PMOS transistor P0, the first PMOS transistor P1 and the third PMOS transistor P3 are short-circuited as the voltage output terminal OUT;

[0051] The voltage input terminal IN is connected to the main clock terminal CLK through the first capacitor C1;

[0052] After the gate terminal of the zeroth PMOS transistor P0 and the drain terminal of the first PMOS tran...

Embodiment 2

[0056] like Figure 4 As shown, the negative voltage charge pump single-stage circuit includes the zeroth NMOS transistor N0, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the first capacitor C1 and the second capacitor C2;

[0057] The source terminal of the zeroth NMOS transistor N0 and the gate terminal of the first NMOS transistor N1 are short-circuited as the voltage input terminal IN;

[0058] The gate end and the source end of the third NMOS transistor N3 are short-circuited with the drain end of the second NMOS transistor N2;

[0059] The drain terminals of the zeroth NMOS transistor N0, the first NMOS transistor N1 and the third NMOS transistor N3 are short-circuited as the voltage output terminal OUT;

[0060] The voltage input terminal IN is connected to the main clock terminal CLK through the first capacitor C1;

[0061] After the gate terminal of the zeroth NMOS transistor N0 and the source terminal of the first NMOS ...

Embodiment 3

[0065] like Figure 5 As shown, a four-phase charge pump circuit comprising the charge pump single-stage circuit of Embodiment 1 or Embodiment 2 is formed by sequentially cascading four charge pump single-stage circuits;

[0066] The voltage output terminal OUT of the single-stage circuit of the previous charge pump is connected to the voltage input terminal IN of the single-stage circuit of the subsequent charge pump;

[0067] The voltage input terminal IN of the single-stage circuit of the first-stage charge pump is used as the input terminal VIN of the four-phase charge pump circuit;

[0068] The voltage output terminal OUT of the fourth-stage charge pump single-stage circuit is used as the output terminal VOUT of the four-phase charge pump circuit;

[0069] The first-phase clock PH1 is connected to the auxiliary clock terminal CLKAUX of the first-stage charge pump single-stage circuit and the third-stage charge pump single-stage circuit;

[0070] The second phase clock P...

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Abstract

The invention discloses a positive voltage charge pump single-stage circuit, which comprises a zeroth PMOS (P-channel Metal Oxide Semiconductor) tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first capacitor and a second capacitor, the drain end of the zeroth PMOS tube and the gate end of the first PMOS tube are in short circuit to serve as a voltage input end; the grid end and the drain end of the third PMOS tube are in short circuit with the source end of the second PMOS tube; source ends of the zeroth PMOS tube, the first PMOS tube and the third PMOS tube are short-circuited to serve as a voltage output end. The voltage input end is connected with a main clock end through the first capacitor. The grid end of the zeroth PMOS tube and the drain end of the first PMOS tube are connected with the grid end and the drain end of the second PMOS tube in a short circuit mode and then connected with an auxiliary clock end through the second capacitor. The invention further discloses a negative voltage charge pump single-stage circuit and a four-phase charge pump circuit. According to the single-stage circuits, the transmission tube in the charge pump single-stage circuit can be prevented from being always in a conducting state without depending on front and rear stages, the voltage resistance requirements of all MOS tubes in the charge pump single-stage circuit are low, high-voltage tubes can not be used, and the area of the charge pump single-stage circuit can be reduced.

Description

technical field [0001] The invention relates to semiconductor circuit technology, in particular to a positive voltage charge pump single-stage circuit, a negative voltage charge pump single-stage circuit and a four-phase charge pump circuit. Background technique [0002] A charge pump circuit can provide a pump voltage of a higher voltage level based on a reference voltage. The voltage level of the pump voltage may be several times the voltage level of the reference voltage. The charge pump circuit can be applied in various electronic devices, such as non-volatile memory, display driver and so on. [0003] The four-phase charge pump circuit is formed by cascading four charge pump single-stage circuits. like figure 1 As shown, the traditional charge pump single-stage circuit includes the zeroth PMOS transistor PMO, the first PMOS transistor PM1, the first capacitor C1, and the second capacitor C2; the drain terminal of the zeroth PMOS transistor P0 and the gate terminal of...

Claims

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Application Information

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IPC IPC(8): H02M3/07
CPCH02M3/073
Inventor 冯国友
Owner PUYA SEMICON SHANGHAI CO LTD
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