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Chip, chip optimization method and electronic equipment

A chip and sub-module technology, applied in the field of chips, chip optimization methods and electronic equipment, can solve the problems of related circuit failure, chip performance reduction, chip failure, etc., and achieve the effect of increasing the number of settings, improving the availability rate, and increasing the number

Pending Publication Date: 2022-02-15
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Process defects can lead to failure of related circuits, thereby causing the failure of the entire chip or reducing the performance of the chip, which also reduces the availability of the chip
[0003] Therefore, the defects in the current process are likely to cause the problem of low availability of dedicated multi-logic and large memory chips.

Method used

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  • Chip, chip optimization method and electronic equipment
  • Chip, chip optimization method and electronic equipment
  • Chip, chip optimization method and electronic equipment

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0041] see figure 1 , the embodiment of the present invention provides a chip 300, including: an instantiation module 301, a common logic module 302 and a bypass module 303, wherein the instantiation module 301 and the common logic module 302 are connected, and the instantiation module 301 is also connected through the bypass module 303 is connected to the common logic module 302 .

[0042] The instantiation module 301 is configured to realize preset processing functions. Specifically, the instantiation module 301 includes multiple identical instantiation units, and each instantiation unit can implement a corresponding function or logic. The preset processing function is determined by the type of the chip 300, which is well known to those skilled in the art, and will not be described in detail in this embodiment.

[0043]The working mode realized by each instantiation unit in the instantiation module 301 in this embodiment is similar to a large number of repeated units in th...

no. 2 example

[0058] see image 3 , A chip optimization method is provided in the embodiment of the present invention. For the relevant explanation and meaning of the terms in this embodiment, please refer to the above-mentioned first embodiment. Specifically, the method includes:

[0059] Step S10: Based on the realizability of functions and logic, determine the instantiation module and common logic module of the chip; wherein, the common logic module is shared by the instantiation unit of the instantiation module, and the instantiation module is used for Realize the preset processing function.

[0060] In step S10, when determining the instantiation module of the chip, the logic that can be shared in the instantiation unit in the instantiation module should be separated as much as possible to form a separate common logic module. Thus, the instantiation module and the common logic module are divided into two area settings, the instantiation area and the common logic area. Since the commo...

no. 3 example

[0075] Based on the same inventive concept, this embodiment also provides an electronic device, including a processor and a memory, the memory is coupled to the processor, the memory stores instructions, and when the instructions are executed by the processor During execution, the electronic device is made to execute the steps of any one of the methods in the above-mentioned second embodiment.

[0076] It should be noted that, in the electronic device provided by the embodiment of the present invention, when the instructions are executed by the processor, the specific implementation and technical effects of each step are the same as those of the foregoing method embodiments. For a brief description, this For the parts not mentioned in the embodiments, reference may be made to the corresponding content in the foregoing method embodiments.

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PUM

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Abstract

The invention discloses a chip, a chip optimization method and electronic equipment. The chip comprises an instantiation module, a public logic module and a bypass module, wherein the instantiation module is configured to be used for realizing a preset processing function, and the instantiation module comprises a plurality of same instantiation units; the public logic module is configured to control the instantiation module and be shared by the instantiation unit; and the bypass module is configured to be used for closing the abnormal instantiation unit in the instantiation module. According to the invention, the availability of the chip can be improved under the condition of the same process yield.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a chip, a chip optimization method and electronic equipment. Background technique [0002] For some dedicated multi-logic and large-storage chips, in order to improve data bandwidth and application-level performance, most of them will choose to repeatedly instantiate a large number of algorithm cores or storage units in the chip. For example, algorithmic multi-array stacking, storage multi-array stacking high-bandwidth multi-core computing chips, etc. These types of chips tend to have larger areas, and from the perspective of chip yield, the larger the chip area, the greater the probability of process manufacturing defects in each chip. Process defects can lead to failure of related circuits, thereby causing the failure of the entire chip or reducing the performance of the chip, which also reduces the availability of the chip. [0003] Therefore, defects in the curr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/398G06F115/12
CPCG06F30/398G06F2115/12
Inventor 李伟
Owner XI AN UNIIC SEMICON CO LTD
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