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Semiconductor chip

A semiconductor and chip technology, applied in the field of semiconductor chips, can solve the problem of reducing the overall area of ​​the chip, to achieve the effect of preventing interference and adverse effects, reducing the overall area, and enhancing the isolation effect

Active Publication Date: 2022-02-18
SG MICRO
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In order to solve the above technical problems, the present invention provides a semiconductor chip, which can effectively reduce the overall size of the chip while preventing noise from interfering with the internal control circuit of the chip. area

Method used

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  • Semiconductor chip
  • Semiconductor chip

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Embodiment Construction

[0027] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. Preferred embodiments of the invention are shown in the accompanying drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention.

[0029] Hereinafter, the present invention will be described in detail with reference t...

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Abstract

The invention discloses a semiconductor chip, which comprises: an internal control circuit layout area, where an internal control circuit is arranged in the internal control circuit layout area; an I / O device layout area, wherein an I / O device is arranged in the I / O device layout area; the isolation strip that is arranged at the junction of the internal control circuit layout area and the I / O device layout area and used for isolating noise interference generated by the I / O device, where at least two side edges of the I / O device layout area are adjacent to the side edges of the semiconductor chip. According to the invention, the overall area of the chip is effectively reduced under the condition of preventing noise from interfering a control circuit in the chip.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a semiconductor chip. Background technique [0002] The BCD process is a process for fabricating a bipolar junction transistor (Bipolar Junction Transistor, BJT), a complementary metal oxide semiconductor (CMOS device) and a diffused metal oxide semiconductor (DMOS device) on the same chip. [0003] In the high-voltage BCD process, the high-power I / O devices with high-frequency operation will generate unnecessary noise during the working process, which will interfere with the internal control circuit of the chip and cause malfunction, thereby affecting the function and performance of the chip. In order to prevent the noise generated by the high-power I / O devices in the chip from interfering with and adversely affecting the internal control circuit, and to prevent the I / O device from latching up with the internal control circuit during chip operation, it is neces...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L27/06
CPCH01L27/0207H01L27/06
Inventor 王巍
Owner SG MICRO
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