Program running method supporting multi-instruction-set system structure, computer equipment and system

A program running and integrated system technology, applied in the direction of machine execution devices, register devices, etc., to achieve the effect of small implementation overhead, low hardware implementation overhead, correctness and speed guarantee

Pending Publication Date: 2022-03-01
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The patent solves how to reduce the hardware overhead of the decoder in the multi-instruction set processor, and does not involve the implementation of the multi-instruction set architecture

Method used

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  • Program running method supporting multi-instruction-set system structure, computer equipment and system
  • Program running method supporting multi-instruction-set system structure, computer equipment and system
  • Program running method supporting multi-instruction-set system structure, computer equipment and system

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Embodiment Construction

[0036] Such as figure 1 As shown, the program running method of this embodiment supporting multiple instruction set architecture (referred to as mArch) includes:

[0037] 1) After power-on reset, reset the processor status register to the encoding corresponding to the default instruction set architecture; see figure 1 , the various instruction set architectures in this embodiment are Arch_1, Arch_2, ..., Arch_N, wherein N>1; the default instruction set architecture is Arch_n, and the code corresponding to the default instruction set architecture is n-1.

[0038] 2) Start fetching instructions from the address specified by the reset address register defined by the default instruction set architecture;

[0039] 3) using the instructions in the default instruction set architecture, respectively setting the control registers and configuration registers defined by the specification of the default instruction set architecture;

[0040] 4) When the binary application program needs ...

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Abstract

The invention discloses a program running method supporting a multi-instruction-set system structure, computer equipment and a system. The method comprises the steps that power-on reset starts instruction fetching execution from an address specified by a reset address register defined by a default instruction set system structure, and a control register and a configuration register are set; loading the binary application program when the binary application program needs to be executed; setting a processor state backup register according to an instruction set architecture based on which the binary application program is based; and executing the exception return instruction to read the value of the processor state backup register so as to set the processor state register and enter a user state, and executing the binary application program needing to be executed. Programs of various instruction set system structures can be directly run on the processor, the problems of execution errors, execution speed slowing and the like possibly caused by the translation process do not exist, the various instruction set system structures are supported only in the user mode, the whole stack does not need to support each instruction set system structure, and the processor hardware implementation cost is small.

Description

technical field [0001] The invention relates to processor architecture technology, in particular to a program running method, computer equipment and system supporting multi-instruction set architecture. Background technique [0002] For processor users, the transplantation of the original application program is very labor-intensive and material-intensive when upgrading the processor architecture, especially when the program scale is large, the transplantation cost is higher; in addition, some applications Possibly only executable binaries, not portable. Because of the high cost and difficulty of software migration, processor users usually do not easily replace processors with different architectures. Even if it is the same architecture, in order to achieve software compatibility, backward compatibility must be achieved during the development of the architecture to ensure that previously developed applications can run on processors of the new architecture. Then, when a new ...

Claims

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/3013
Inventor 卢凯王永文隋兵才孙彩霞倪晓强邓全郑重王俊辉雷国庆黄立波郭维郭辉
Owner NAT UNIV OF DEFENSE TECH
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