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A thin film process optimization method for improving fdsoi epitaxial growth

An optimization method and epitaxial growth technology, which is applied in the manufacture of electrical components, circuits, semiconductors/solid-state devices, etc., can solve problems such as uneven epitaxial layer growth, insufficient corrosion, and over-corrosion of the film, so as to avoid the incomplete growth of the top silicon layer , prevent insufficient corrosion, improve the effect of uniformity and integrity

Active Publication Date: 2022-04-22
GUANGDONG GREATER BAY AREA INST OF INTEGRATED CIRCUIT & SYST +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Aiming at the existing processing technology existing in the prior art, it is easy to cause the film to be over-etched or under-etched, and the corner where the gate region is connected to the first layer of top-layer silicon is easy to leave a film, resulting in uneven or incomplete growth of the epitaxial layer The present invention provides a film process optimization method for improving FDSOI epitaxial growth, which can effectively control the film thickness, prevent the film from being over-etched or under-etched, and reduce the connection corner between the gate region and the first top layer of silicon The residual film at the place expands the epitaxial growth window, which can improve the uniformity and integrity of the epitaxial growth

Method used

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  • A thin film process optimization method for improving fdsoi epitaxial growth
  • A thin film process optimization method for improving fdsoi epitaxial growth
  • A thin film process optimization method for improving fdsoi epitaxial growth

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Embodiment 1

[0048] Embodiment 1, when the gate region above the N-type silicon substrate 1 on the field effect transistor includes at least two, and in this embodiment is three, the following processing technology is used to realize the epitaxial growth of the field effect transistor substrate:

[0049] See figure 2 , the thin film processing technology optimization method includes: S1, using the atomic layer deposition amorphous silicon carbon nitride deposition process (ie ALD SiCN) to deposit the first layer of thin film 6 on the upper surface of the N-type silicon substrate and the P-type silicon substrate (see image 3 shown), the first film 6 is amorphous silicon carbon nitride (SiCN), and the deposition thickness is 80Å;

[0050] S2, the mask plate 9 is set on the top of the P-type silicon substrate (see Figure 4 shown);

[0051] S3. First place the substrate with the deposited first layer of thin film in the cleaning machine, and use the pre-cleaning method (i.e. SiCoNi techno...

Embodiment 2

[0059] Embodiment 2, when the gate regions above the N-type silicon substrate 1 and the P-type silicon substrate 2 of the field effect transistor include at least two, and in this embodiment, each includes three, the following processing technology is used to realize the field effect Transistor substrate silicon epitaxial growth:

[0060] The epitaxial growth method above the N-type silicon substrate 1 in this embodiment is the same as steps S1-S8 in Embodiment 1. The epitaxial growth processing method of this embodiment also includes the silicon epitaxial growth above the P-type silicon substrate 2. The specific process steps Including S9 to grow a second epitaxial layer on the top silicon layer above the P-type silicon substrate, see Figure 8 , including: S91, setting a mask plate above the N-type silicon substrate. In this embodiment, after the above steps S1 to S8, a SiGe epitaxial layer has been grown on the N-type silicon substrate. A mask plate is covered above the N-...

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Abstract

The invention discloses a thin film process optimization method for improving FDSOI epitaxial growth, which can reduce the residual thin film at the corner where the gate region and the top layer silicon are connected. The transistor includes a substrate, and an active region and a trench isolation region are distributed on the substrate. , gate area, the substrate includes N-type silicon substrate and P-type silicon substrate, the first layer of top layer silicon is deposited on the upper surface of the active area, and the film processing includes: the upper surface of the N-type silicon substrate and the P-type silicon substrate are The first layer of film is deposited, a mask is set on the top of the first layer of the P-type silicon substrate, the first layer of film above the N-type silicon substrate is etched, and the first layer of the top layer of silicon is deposited on the surface of the first layer. Two layers of top layer silicon, deposit a second layer of film on the surface of the second layer of top layer silicon, etch the second layer of film above the N-type silicon substrate, after etching the second layer of film, deposit a second layer of film on the outer surface of the second layer of top layer silicon A third top layer of silicon is deposited, and the first layer of top silicon, the second top layer of silicon, and the third top layer of silicon are combined to form a first combined top layer of silicon.

Description

technical field [0001] The invention relates to the technical field of transistor processing, in particular to a film process optimization method for improving FDSOI epitaxial growth. Background technique [0002] With the development of integrated circuits, the epitaxial process is widely used. Epitaxial growth is a transistor processing process that grows one or more new single crystals on a single crystal substrate to improve device design flexibility and device performance. Currently, the commonly used Epitaxial growth processes include: decompression epitaxy, low temperature epitaxy, selective epitaxy, liquid phase epitaxy, heterogeneous epitaxy, etc., among which selective epitaxy refers to the arrangement of masks on the substrate, and the opening of single-crystal epitaxy in a certain area on the substrate. The window area where the layer grows, and the area where the mask is left no longer grows the epitaxial layer. [0003] At present, in the FDSOI manufacturing p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02H01L21/84
CPCH01L21/02381H01L21/02532H01L21/02658H01L21/02661H01L21/84
Inventor 苏炳熏叶甜春朱纪军李彬鸿罗军赵杰
Owner GUANGDONG GREATER BAY AREA INST OF INTEGRATED CIRCUIT & SYST