Digital watermark hardware circuit based on DCT (Discrete Cosine Transform)

Abstract

The invention discloses a digital watermark hardware circuit based on DCT (Discrete Cosine Transform). The digital watermark hardware circuit comprises a digital watermark embedding module, a digital watermark extraction module, a watermark RAM (Random Access Memory), a host RAM, an extraction RAM and an embedding RAM, wherein the watermark RAM stores watermark data and transmits the watermark data to the digital watermark embedding module for Arnold scrambling processing, the host RAM stores data of a host image and transmits the data to the watermark embedding module for 2D-DCT processing, and the embedded RAM receives the watermark-embedded data transmitted by the digital watermark embedding module on one hand and reads the data on the other hand. And the extraction RAM is used for receiving the watermark data extracted by the digital watermark extraction module. The invention aims to improve the working frequency and throughput rate while ensuring the information transmission security.

Description

technical field [0001] The invention belongs to the technical field of digital watermarking, and specifically relates to a digital watermarking hardware circuit applied to copyright protection, concealed identification, authentication and secure covert communication. Background technique [0002] With the continuous development of the Internet age, information interaction has become more and more frequent, and the problem of malicious theft of information has become more and more serious. The issue of information security is becoming increasingly prominent, and digital watermarking has attracted much attention as a means of copyright protection and identity authentication. For the information that needs to be encrypted, it can be embedded in the image as a watermark to avoid malicious theft and tampering of the information. Researchers began to hide and encrypt images by embedding watermarks. Digital watermarks are divided into visible watermarks and invisible watermarks. ...

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Problems solved by technology

[0003] Maity et al. proposed a reversible watermarking hardware circuit based on contrast mapping. The design uses a six-stage pipeline architecture. Although the calculation speed is accelerated, the resource consumption is more

In order to reduce resource consumption, Phadikar et al. proposed a hardware architecture of an adaptive quantization index modulation data hiding scheme in the DCT transform domain. Through parallel processing, the design of low power consumption and high data throughput was realized, but the parallel architecture is better than the serial Architecture increases the number of LUTs and registers

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