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NAND gate tree structure

A technology of NOT gate tree and NOT gate, applied in the field of NAND gate tree structure and testing field using the same, can solve problems such as unfavorable miniaturization of semiconductor devices and cost suppression.

Pending Publication Date: 2022-03-22
INST OF MICROELECTRONICS CHINESE ACAD OF SCI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in order to test AC performance, it is sometimes necessary to have spare space within the product for the measurement circuit, as well as a spare pad
Therefore, the enlarged product size is not conducive to the miniaturization and cost suppression of semiconductor devices.

Method used

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  • NAND gate tree structure
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Embodiment Construction

[0018] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0019] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, s...

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Abstract

The invention provides an NAND gate tree structure. The NAND gate tree structure comprises a plurality of NAND gates; wherein the first input end of the first NAND gate is connected with a first input signal, the output end of the first NAND gate serves as the output of the whole NAND gate tree structure, and the second input end of the first NAND gate is connected with the output end of the second NAND gate. The advantages of the present disclosure are that, in order to increase the area of a ring-free oscillator, the input signals are divided into two types for NAND gate tree measurement and ring oscillator, and NAND gate circuits included in the input and output terminals are used in both the two types of the input signals for NAND gate tree measurement and the two types of the input signals for ring oscillator measurement. And output results under the two conditions can be obtained. Therefore, the size of the product does not need to be enlarged, and miniaturization and cost suppression of the semiconductor device are facilitated.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductor manufacturing, in particular to a NAND tree structure and a testing method using it. Background technique [0002] In the ultra-micro-semiconductor process, because the AC performance is important, it is often necessary to use the ring oscillator circuit for measurement and management, because the DC parameter values ​​​​and AC properties of the ultra-micro process and semiconductor components are not equal. However, in order to test AC performance, it is sometimes necessary to leave room for the measurement circuit inside the product, as well as to have a spare pad. Therefore, the size of the product enlarged in this way is not conducive to miniaturization and cost suppression of semiconductor devices. Contents of the invention [0003] The purpose of the present disclosure is to propose a NAND tree structure aimed at the shortcomings of the above-mentioned prior art, and the pu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/26
CPCG01R31/2607
Inventor 李相惇张欣杨红杨涛李俊峰王文武
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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