M-LVDS drive circuit for preventing bus electric leakage

Abstract

The invention discloses an M-LVDS (M-low voltage differential signaling) driving circuit for preventing bus electric leakage, which belongs to the field of I/O (input/output) ports of integrated circuits and comprises a secondary power supply, a main driving circuit connected with the secondary power supply, a switching tube and a floating lining circuit. The secondary power supply comprises two stages of power supplies which respectively supply power to the main driving circuit so as to accurately control the switching tube and reduce the noise influence of the switching tube on the power supply; the floating lining circuit is connected with the switching tube, the lining bias effect of the switching tube is reduced, bus current is effectively prevented from flowing back to the power supply when the power supply is powered down, and the working efficiency of the switching tube is improved. Input control signals in a traditional M-LVDS drive circuit are processed through the secondary power supply, and interference of switching signals on the power supply can be isolated. According to the M-LVDS circuit, a current backflow prevention structure is arranged in the M-LVDS circuit, and a substrate structure of a PMOS switching tube in the traditional M-LVDS circuit is replaced by an NMOS pair in a diode connection mode, so that the substrate bias effect of the PMOS switching tube is reduced, hidden communication between a port signal and a power supply during cold backup is avoided, and electric leakage of a bus is prevented.

Description

technical field [0001] The invention relates to the technical field of integrated circuit I / O ports, in particular to an M-LVDS drive circuit for preventing bus leakage. Background technique [0002] With the integration of signal transmission technologies such as LVDS (Low-Voltage Differential Signaling, low voltage differential signal), M-LVDS (multipoint LVDS), LV-PECL (Low Voltage Positive Emitter-Couple Logic, low voltage positive emitter coupling logic) With the development of the field of circuit I / O port technology, the application of M-LVDS transceivers is becoming more and more extensive. The driving circuit is directly connected to various standard types of digital buses, and the I / O ports send and receive data to the bus. [0003] In an M-LVDS transceiver, a typical driving circuit structure is usually as follows figure 1 As shown, two pairs of PMOS switch tubes are turned on alternately. When one pair of switch tubes is turned off, the high level of the drive s...

AI Technical Summary

Problems solved by technology

For this method, the voltage drop between the power supply VCC and the bias voltage Vsub will not exceed the turn-on voltage of the diode (generally VCC-0.3V), and in the M-LVDS driver, the voltage common mode of the bus port The value is generally about VCC / 2. In this application scenario, the substrate voltage of the PMOS switch will be relatively high, which will bring about a certain lining bias effect, which will increase the turn-on voltage of the PMOS switch. Under the same size, the passing current Reduced ability

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