Capacitance test structure and forming method thereof

Abstract

The invention discloses a capacitance test structure and a forming method thereof, and the forming method comprises the steps: providing a semiconductor substrate, forming a well region in the semiconductor substrate, and enabling the well region to be doped with a first type of foreign ions; an isolation doped region surrounding the well region is formed in the semiconductor substrate, the isolation doped region is doped with impurity ions of a second type, and the second type is opposite to the first type; and forming a capacitance testing device in the well region. The isolation doped region surrounds the well region, and the types of the impurity ions doped in the isolation doped region are opposite to those of the impurity ions doped in the well region and the semiconductor substrate, so that the well region and the semiconductor substrate outside the isolation doped region are not in direct contact or are isolated; the influence of parasitic capacitance of an external circuit on a capacitance test result when the well region is in direct contact with the semiconductor substrate can be prevented, so that the accuracy of the capacitance test result is improved.

Description

technical field [0001] The present application relates to the field of semiconductor testing, in particular to a capacitance testing structure and a forming method thereof. Background technique [0002] Existing wafers used for integrated circuit production are generally substrates doped with P-type impurities, and then various devices to be tested for capacitance testing are fabricated on the P-type substrates, such as MOS transistors (Metal-oxide- semiconductor) as an example, since the well region of the NMOS transistor is also P-type, that is, the doping type is the same as that of the P-type substrate, when testing the capacitance of the gate dielectric layer, the P-type well region of the NMOS transistor will be in contact with the P-type substrate Directly connected, and the P-type substrate will be connected to the test machine and other external circuits. When we use the probe to test the capacitance of the NMOS transistor, it will inevitably bring in the parasitic ...

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Problems solved by technology

[0002] Existing wafers used for integrated circuit production are generally substrates doped with P-type impurities, and then various devices to be tested for capacitance testing are fabricated on the P-type substrates, such as MOS transistors (Metal-oxide- semiconductor) as an example, since the well region of the NMOS transistor is also P-type, that is, the doping type is the same as that of the P-type substrate, when testing the capacitance of the gate dielectric layer, the P-type well region of the NMOS transistor will be in contact with the P-type substrate Directly connected, and the P-type substrate will be connected to the test machine and other external circuits. When we use the probe to test the capacitance of the NMOS transistor, it will inevitably bring in the parasitic capacitance of the external circuit, which will directly affect the gate. The accuracy of the test results of dielectric layer capacitance

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