Configuration circuit of register and integrated circuit chip

Abstract

The invention discloses a register configuration circuit, which comprises a clock switching module used for outputting a target clock signal consistent with a clock signal of a target function module according to a target control signal when a register of the target function module in a target integrated circuit chip needs to be configured; the asynchronous bridge is connected with the clock switching module and is used for carrying out clock domain crossing processing on a register configuration request signal in a source clock domain sent by a target host so as to convert the register configuration request signal in the source clock domain into a register configuration request signal in a target clock domain; and the protocol processing module is connected with the asynchronous bridge and is used for configuring a target register according to the register configuration request signal in the target clock domain. By means of the register configuration circuit, the metastable state problem existing in the register configuration circuit can be solved, and the structural complexity and the area overhead of the register configuration circuit can be reduced.

Description

technical field [0001] The invention relates to the technical field of power electronics, in particular to a register configuration circuit and an integrated circuit chip. Background technique [0002] Many functional modules are usually set in a large integrated circuit chip, and these functional modules often include multiple registers. In order to make these functional modules work normally, it is usually necessary to configure appropriate values ​​for these registers. Since these functional modules may be in different clock domains, when the system host configures the registers of these functional modules, the problem of clock crossing needs to be considered. In the prior art, the following two circuit structures are often used to configure registers. [0003] See figure 1 , figure 1 A structural diagram of a configuration circuit for an existing register, in figure 1 In the circuit structure shown, the bus protocol processing circuit is directly used to configure an...

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Problems solved by technology

However, the process of processing each clock signal in this configuration circuit is very complicated, not only need to consider the different processing methods of single-bit signal and multi-bit signal, but also consider the speed of the source clock signal and target clock signal, Especially when multi-bit signals are synchronously processed, FIFO (First Input First Output, first-in-first-out) memory is required, which leads to a large area overhead of the register configuration circuit

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