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Preparation method of semiconductor device and semiconductor device

A semiconductor and device technology, which is applied in the preparation of semiconductor devices and the field of semiconductor devices, can solve the problems that Wafer central GaN and edge GaN cannot be etched at the same time, the etching speed of the edge and the center is inconsistent, and the performance of the device is affected. Achieve the effect of avoiding back hole metal layering, avoiding back hole collapse, and ensuring device yield

Active Publication Date: 2022-07-29
深圳市时代速信科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this process has the following problems: the wafer (wafer) is very thin after thinning, the stress causes the wafer to warp, the etching speed of the edge and the center is inconsistent, and it often occurs that the central GaN and the edge GaN of the wafer cannot be etched at the same time
The result of over-etching may be back hole collapse and back hole metal delamination, which will affect the device yield and device performance.

Method used

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  • Preparation method of semiconductor device and semiconductor device
  • Preparation method of semiconductor device and semiconductor device
  • Preparation method of semiconductor device and semiconductor device

Examples

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no. 1 example

[0061] see figure 1 , this embodiment provides a method for preparing a semiconductor device 100 for preparing the semiconductor device 100 , the method does not have the problem of over-etching after the etching is completed, and avoids the possible collapse of the back hole and the occurrence of the over-etching process. Technical problems such as back hole metal delamination ensure the device yield and device performance.

[0062] The manufacturing method of the semiconductor device 100 provided in this embodiment includes the following steps:

[0063] S1 : epitaxially growing the epitaxial material layer 120 on the substrate 110 .

[0064] see in combination figure 2 Specifically, the nucleation layer 121, the first epitaxial layer 122, the second epitaxial layer 123 and the cap layer 124 may be sequentially deposited on the substrate 110 by MOCVD (chemical vapor deposition), wherein the substrate 110 may be SiC, Si, Sapphire, etc., preferably SiC, the nucleation layer...

no. 2 example

[0084] see Figure 10 , this embodiment provides a method for fabricating a semiconductor device 100, the basic steps, processes and technical effects of the method are the same as those in the first embodiment. Corresponding content in the examples.

[0085] This embodiment provides a method for fabricating a semiconductor device 100, including the following steps:

[0086] S1 : epitaxially growing the epitaxial material layer 120 on the substrate 110 .

[0087] Specifically, the nucleation layer 121 , the first epitaxial layer 122 , the second epitaxial layer 123 and the cap layer 124 may be sequentially deposited on the substrate 110 by MOCVD (Chemical Vapor Deposition). After the epitaxial material layer 120 is formed, a passivation layer 125 can also be grown on the surface of the epitaxial material layer 120. The passivation layer 125 can be made of SiN, and SiN forms dangling bonds with the surface of the material to achieve surface passivation and solve the current p...

no. 3 example

[0103] see Figure 14 , this embodiment provides a method for fabricating a semiconductor device 100, the basic steps, processes and technical effects are the same as those in the second embodiment. For a brief description, for the parts not mentioned in this embodiment, refer to the second Corresponding content in the examples.

[0104] This embodiment provides a method for fabricating a semiconductor device 100, including the following steps:

[0105] S1 : epitaxially growing the epitaxial material layer 120 on the substrate 110 .

[0106] S2 : forming a conductive region 130 in a partial region of the epitaxial material layer 120 .

[0107] Specifically, the first implantation region may be formed in a partial region of the epitaxial material layer 120 by Si ion implantation, and then the first implantation region may be activated after high temperature annealing to form the conductive region 130 .

[0108] Wherein, steps S1-step S2 are the same as those in the second em...

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Abstract

The invention provides a preparation method of a semiconductor device and a semiconductor device, and relates to the technical field of semiconductors. The semiconductor device includes a substrate, an epitaxial material layer, a source electrode, a drain electrode, a gate electrode and a back metal layer, and is arranged in the epitaxial material layer. A conductive area is formed in a part of the area of ​​the semiconductor device, then the front side process of the semiconductor device is completed, and finally the back side process is completed, and a through hole is formed by etching on the substrate, and a back gold layer is formed. Compared with the prior art, the present invention makes part of the epitaxial material layer have conductive properties, so that the epitaxial material layer does not need to be etched when the source through hole is formed, and the epitaxial material layer acts as an etching stop layer, and does not need to be etched after the etching is completed. There is the problem of over-etching of metal electrodes, which avoids technical problems such as back hole collapse and back hole metal delamination that may be caused by the over-etching process, and ensures device yield and device performance.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a method for preparing a semiconductor device and a semiconductor device. Background technique [0002] GaN material has the characteristics of high electron mobility and high breakdown electric field. High electron mobility transistors based on GaN / AlGaN have excellent characteristics of high voltage operation (50V working voltage), high temperature resistance, high frequency and high efficiency. GaN HEMT devices are the core components of 4G and 5G communication base stations, electronic countermeasures and phased array mines. Power amplifiers designed based on GaN HEMT devices play a vital role. [0003] In the prior art, through the backside opening process, the backside is opened below the ohmic metal of the device, and the sidewall of the hole is metallized, and the source of the device is grounded through the backhole metal. The conventional process i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L21/335H01L29/778
CPCH01L29/0657H01L29/0684H01L29/66462H01L29/778
Inventor 杨天应许建华
Owner 深圳市时代速信科技有限公司
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