Satellite load BRAM anti-radiation design method based on position constraint

Abstract

The invention provides a satellite load BRAM anti-radiation design method based on position constraint, and the method comprises the steps: adding a BRAM position constraint script, controlling EDA software to enable the BRAM to be arranged at a specified position, and employing a method of adding region constraint to prevent any two key function modules from being distributed in the same wiring region. According to the method, the probability of simultaneous error of a plurality of functional modules in the triple modular redundancy design of the key functional modules due to single event upset of the BRAM is fundamentally reduced, the working reliability of the satellite load in the space irradiation environment is improved, and reference is provided for more comprehensively improving the radiation-proof reinforcement design of the satellite-borne FPGA.

Description

technical field [0001] The invention belongs to the technical field of FPGA reliability, and relates to a radiation-resistant design method of a satellite load BRAM based on position constraints. Background technique [0002] SRAM-type FPGAs are fast in operation and flexible in design. Compared with traditional aerospace-grade devices, SRAM-type FPGAs have great advantages, but they are very prone to single-event effects in space irradiation environments. Space single-event effects hinder SRAM-type FPGAs from being used in space missions. It is very necessary to design protection and reinforcement for bottlenecks that are more widely used. Especially for the BRAM memory, because the data stored in it has been in dynamic applications, it is difficult to eliminate the accumulation of spatial single event upset (SEU) through traditional refresh operations, which is one of the main causes of spatial single event events in SRAM FPGAs. . [0003] The inversion of a single confi...

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Problems solved by technology

[0003] The inversion of a single configuration bit of the FPGA may cause simultaneous errors in multiple functional modules in the redundant design of key functional modules, resulting in the failure of all key logic

Traditional anti-single event effect reinforcement design methods, such as triple-mode redundancy (TMR), error detection and correction coding (EDAC) technology, readback refresh, etc., cannot fundamentally solve this problem, and further research is still needed Strategies to improve the anti-single event upset ability of traditional design to improve the fault tolerance of FPGA routing resources to single event effect faults, so as to ensure the reliable operation of key functional modules in electronic devices in the space radiation environment

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