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Formation method of semiconductor structure

A semiconductor, patterning technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., to maintain stress and improve performance

Pending Publication Date: 2022-05-13
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the technology of germanium-silicon channel devices still needs to be continuously improved.

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Experimental program
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Embodiment Construction

[0036] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space, and are not limited to direct contact.

[0037] As mentioned in the background, the performance of the semiconductor structure formed by using the existing SiGe channel device technology needs to be improved urgently. Now combine a semiconductor structure for description and analysis.

[0038] Figure 1 to Figure 2 It is a schematic cross-sectional view of the formation process of a semiconductor structure.

[0039] Please refer to figure 1 , providing a substrate 101; forming a channel material layer 102 on the substrate 101; forming a patterned layer 103 on the channel material layer 102, and the patterned layer 103 exposes part of the surface of the channel material layer 102 .

[0040] Please refer to figure 2 , using the patterned layer 103 as a mask, etching the channel material layer 101 and the substrate 101 to form fi...

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Abstract

A method for forming a semiconductor structure comprises the steps that a substrate is provided, and the substrate comprises a first region and a first fin part located on the surface of the first region; forming an isolation prefabricated layer on the surface of the substrate, wherein the isolation prefabricated layer is also located on the side wall of the first fin part; the first fin part is etched, a plurality of openings are formed in the isolation prefabricated layer, and the isolation prefabricated layer is exposed out of the side walls of the openings; forming a barrier layer on the side wall of the opening; and forming a channel layer in the opening. Since the channel layer is formed by growing the channel layer material at the bottom of the opening and is not required to be obtained by etching after forming a channel material layer, the stress of the channel layer is determined by material growth, the stress release caused by subsequent etching is avoided, the stress of the channel layer is maintained, and the performance of the device is improved. The improvement of the mobility of carriers of the channel layer is not affected, and the performance of the device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the further development of semiconductor technology, after the feature size of transistors is reduced to the nanometer scale, proportional reduction technology is facing more and more severe challenges, such as: mobility degradation, source-drain punch-through leakage, hot carrier effect, etc. Among them, mobility degradation is the main difficulty affecting the speed improvement of integrated circuits. By increasing the mobility of carriers in the channel, it can compensate for the mobility degradation caused by factors such as the Coulomb interaction caused by high doping of the channel, the increase in the effective electric field strength caused by the thinning of the gate dielectric, and the enhancement of interface scattering. [0003] Strained silicon technology introduc...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/78
CPCH01L29/66803H01L29/785H01L29/7849
Inventor 苏博吴汉洙施雪捷
Owner SEMICON MFG INT (SHANGHAI) CORP