Chip repairing method, repairing device and chip
A repair method and chip technology, applied in static memory, instruments, etc., can solve problems such as increased production costs, faulty cells in memory, and reduced chip yield, and achieve the effects of improving repair capability, satisfying power consumption, and improving flexibility
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[0089] Figure 9 This is a schematic diagram of the structure of chip repair in this embodiment.
[0090] In the CP test phase of the chip, the main memory SRAM is accessed through the built-in self-test (MBIST, Memory Built-In Self-Test) technology, the main memory SRAM is accessed, the operation results are compared with the expected, and the main memory is judged by an algorithm. Whether the SRAM is faulty;
[0091]If there is a fault, write the fault address of the faulty unit of the main memory SRAM into the eFuse memory for subsequent repair of the main memory SRAM;
[0092] In the repair stage, every time the chip is powered on, the fault address stored in the eFuse memory is read out through the built-in self-repair (BISR, Built In Self Repair) circuit, and after processing, it is mapped to a separate built-in redundant memory The redundant address of the redundant unit is used to replace the faulty address with the redundant address, so as to achieve the purpose of ...
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