Neural network accelerator fault vulnerability assessment method based on hardware feature information

Abstract

The invention discloses a neural network accelerator fault vulnerability assessment method based on hardware feature information, which comprises the following steps: extracting hardware information features of a neural network operating on a hardware accelerator, the information features comprising features of the neural network in normal operation and information features of the neural network in fault attack; and modeling fault attack by using the extracted information features, predicting the influence of the fault on an actual neural network hardware accelerator through a fault distribution simulation and fault probability simulation method, and judging the vulnerability of the neural network when the neural network is faced with the fault attack through an interlayer search method. According to the method, an existing hardware fault vulnerability assessment framework is improved, and the accuracy of fault simulation is improved through a software and hardware integrated verification method while the fine granularity is optimized. The improved method has a good effect in evaluating common hardware fault attacks, and has a certain application value in the field of hardware fault evaluation.

Description

technical field [0001] The invention belongs to the fields of hardware failure safety evaluation and the like, and in particular relates to a failure vulnerability evaluation method of a neural network accelerator based on hardware feature information. Background technique [0002] Deep learning powers a wide variety of edge devices, and the widespread use of neural network hardware accelerators has raised concerns about their security and robustness. Although Deep Neural Network (DNN) models have evolved to outperform humans in terms of prediction, their predictive behavior involves a complex training process and adaptation to a large number of weight parameters, which makes the computation of neural networks unexplainable sex. When errors (whether artificial or natural) occur in the computation of DNN models deployed on hardware (such as FPGAs, ASICs, etc.), the inference process of neural networks is disrupted. This makes the fault tolerance of different DNN models a to...

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Problems solved by technology

Such simplistic assumptions are likely to be mismatched with actual fault attack scenarios on DNN hardware, leading to lower accuracy of results given by these evaluation schemes.

In addition, most of the curr

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