Flow control mechanism-oriented deadlock-free extensible interconnection bare core architecture

Abstract

The invention provides a deadlock-free extensible high-speed interconnection bare core framework facing a flow control mechanism. The architecture aims at solving the problem that an on-chip and inter-chip integrated network lacks a unified architecture standard when facing the technical problems of data routing deadlock, resource limitation, cross-clock domain inter-chip transmission and the like. The interconnection bare chip architecture generally comprises a network-on-chip and two expansion port controllers, each expansion port controller is composed of a bypass controller, a bandwidth sharing allocation arbitration unit and a synchronous controller, the bandwidth sharing allocation arbitration unit is a core component for realizing an inter-chip Virtual-Cut-Through flow control mechanism, and the bandwidth sharing allocation arbitration unit is a core component for realizing an inter-chip Virtual-Cut-Through flow control mechanism. And working and running under the guidance of the state machine. According to the invention, the compromise relationship between resources and performance faced by 2D packaging is well coordinated, the modular design of the deadlock-free multi-bare-chip integrated system based on the Virtual-Cut-Through flow control mechanism is realized, and the expandability and the design flexibility are good.

Description

technical field [0001] The invention relates to the technical field of digital integrated circuits, in particular to a deadlock-free scalable interconnection bare-chip architecture oriented to an inter-chip Virtual-Cut-Through flow control mechanism. Background technique [0002] With the development of digital integrated circuits, system on chip (System on Chip, SoC, refers to the integration of multiple functional modules on the same silicon chip) has almost become a necessary solution to achieve high-performance systems. Scale to meet user demand for product performance. However, limited by factors such as processing technology, Moore's Law (that is, the law that the number of transistors that can be accommodated on an integrated circuit doubles every 24 months) is gradually failing, which makes it difficult to expand the scale of integrated circuits on a single silicon wafer. Costs and development cycles become extremely high. [0003] In the future, integrated circuit...

AI Technical Summary

Problems solved by technology

However, limited by processing technology and other factors, Moore's Law (that is, the law that the number of transistors that can be accommodated on an integrated circuit doubles every 24 months) is gradually failing, which makes it impossible to expand the scale of integrated circuits on a single silicon chip. Costs and development cycles become extremely high

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