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Instruction programmable buffer design system based on processor debugging architecture

A technology for designing systems and processors, applied in the field of instruction programmable buffer design systems, can solve problems such as differences in results and processor interruptions, and achieve the effects of simple structure, high flexibility, and easy operation

Pending Publication Date: 2022-07-01
中电科申泰信息科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Interactive debugging is intrusive to the processor's operation, and results may vary between debug mode and full-speed operation

Method used

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  • Instruction programmable buffer design system based on processor debugging architecture
  • Instruction programmable buffer design system based on processor debugging architecture
  • Instruction programmable buffer design system based on processor debugging architecture

Examples

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Embodiment Construction

[0020] like figure 1 As shown in the block diagram of the architecture, this embodiment provides an instruction programmable buffer design system based on the processor debugging architecture. The processor core system built in the design system is the basic framework of the application, serving the instruction programmable buffer. The processor core system includes a debug interface module, an interface conversion module, and a debug module, wherein an instruction programmable buffer design is added to the hardware design of the debug module to provide software debuggers with downloading instructions to the processor core in the debug mode. the means of execution;

[0021] The debug interface module implements the JTAG interface conforming to the IEEEStd 1149.1-2013 protocol standard, including five interface signals of TCK, nRESET, TMS, TDI and TDO. TCK and nRESET are clock and reset, TMS is used for controller JTAG state machine jump, TDI and TDO are serial input and outpu...

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Abstract

The invention relates to an instruction programmable buffer area design system based on a processor debugging architecture, and the processor debugging architecture is generally composed of a debugging interface module, an interface conversion module, a debugging module and a processor core. The interface conversion module converts serial data into parallel data and achieves access to the debugging module, and software debugging personnel control the debugging process of the processor core through the debugging module. According to the invention, the design of the instruction programmable buffer area is realized in the hardware design of the debugging module, so that software debugging personnel can quickly and conveniently download the instruction to the processor core for operation. Three different instruction programmable buffer designs are provided, debugging can be carried out independently and can also be matched with one another according to different use scenes, and debugging of the processor core is achieved more efficiently.

Description

technical field [0001] The invention relates to the technical field of processor core design, in particular to an instruction programmable buffer design system based on a processor debugging architecture. Background technique [0002] In the processor design process, without a fully functional debug system, the designer's understanding and control of the current state of the processor will drop dramatically as the design progresses from tool simulation to hardware verification to final silicon implementation. , the controller's internal state at runtime is equivalent to a "black box" to the designer. The development and debugging of processor software and hardware will be greatly limited due to the lack of debugging methods. [0003] For embedded platforms, the debugger software generally runs on the host PC, and the debugged processor is often on the embedded development board, which is a typical scenario of cross-compilation and remote debugging. The debugger software ne...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36
CPCG06F11/366
Inventor 孙维东邵健胡鹏孙诚
Owner 中电科申泰信息科技有限公司
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