6 results about "Interactive debugging" patented technology

An integrated circuit (IC) design may be received by a first process. First reset domain crossing (RDC) analysis may be performed by the first process on the IC design to generate first RDC analysis results. A set of processes may be spawned by the first process, where a second process in the set of processes may read the first RDC analysis results, obtain information for an RDC scenario from the first process, perform second RDC analysis on the IC design based on the information for the RDC scenario to obtain second RDC analysis results, and send the second RDC analysis results to the first process. The second RDC analysis results received from the set of processes may be merged by the first process to obtain merged RDC analysis results.

This invention discloses a motion control table script execution system supporting online programming and debugging, relating to the field of motion control software development. The system includes: an integrated script execution engine, which integrates a C language interpreter and a motion control function library within a single execution environment, used to directly parse script text conforming to C language syntax rules and convert it into control instructions for the motion control table; a concurrent execution and isolation management unit, used to create and maintain an independent execution context with a complete lifecycle for each user script, and to schedule multiple execution contexts to run concurrently and in isolation within the script execution engine; and an online interactive debugging interface, used to receive external debugging instructions during script execution and control the script execution engine to switch between full-speed running mode and interactive debugging mode. This solution can significantly improve the development efficiency, operational safety, and task processing capabilities of motion control systems.

The invention provides a data development debugging method and device, equipment, a storage medium and a program product. Relates to the technical field of data development. The method comprises the following steps: in response to a received debugging request initiated by a user through a data development platform, allocating computing resources based on the debugging request and starting an interactive debugging environment instance; the debugging request comprises a Python operator code to be debugged; executing the Python operator code to be debugged in the interactive debugging environment instance, and displaying a code execution result and a variable value; and backfilling the debugged Python operator code in the interactive debugging environment instance into a static code editor of the data development platform. According to the method provided by the invention, the code execution state can be checked in real time, the code writing and debugging process is deeply integrated, environment switching and manual operation are avoided, and human errors are reduced; through a reasonable resource management and scheduling mechanism, it is ensured that computing resources can be fully utilized in the starting and running process of the interactive debugging environment instance, and resource waste is avoided.

The invention relates to a visual design and simulation method and system for a complex digital system based on a graphical hardware description language HDL-X. The method comprises the steps that the graphical hardware description language HDL-X and a visual simulation environment based on XML expansion SVG are constructed, and a graphical model is constructed through an automatic anchor point connection technology; defining device functions through four modes of device basic information, a truth table, a logic expression and a latch; the graphical model is converted into executable function description based on an HDL-X interpreter, a simulation and visualization real-time linkage mechanism is adopted, a signal path is dynamically highlighted in a graphical interface, waveform changes are synchronously displayed, a collaborative analysis environment of graphical waveforms and structural topology is formed, and interactive debugging of breakpoint setting and dynamic parameter modification is supported; the matched simulation verification system integrates a graphical design module, a device library management module, a function definition module, a compiling interpretation module, a simulation engine module and a visual linkage module; according to the method, the defects of insufficient design visualization, simulation debugging splitting and difficulty in cross-module signal tracking in the prior art are overcome.

The application relates to a complex digital system visual design and simulation method and system based on a graphical hardware description language HDL-X, the method constructs a graphical hardware description language HDL-X and a visual simulation environment based on XML extended SVG, constructs a graphical model through an anchor point automatic connection technology, and defines device functions through four modes of device basic information, a truth table, a logic expression and a latch; the graphical model is converted into an executable function description based on an HDL-X interpreter, a simulation and visual real-time linkage mechanism is adopted, signal paths are dynamically highlighted in a graphical interface, and waveform changes are synchronously displayed, a collaborative analysis environment of graphical waveforms and structure topologies is formed, interactive debugging of breakpoint setting and dynamic parameter modification is supported; a matching simulation verification system integrates graphical design, device library management, function definition, compilation and interpretation, a simulation engine and a visual linkage module; the application solves the defects of design visualization deficiency, simulation debugging fragmentation and cross-module signal tracking difficulty in the prior art.

A data processing system includes compile time logic configured to generate configuration files for applications executing on reconfigurable processors, and execution flow logic configured to manage execution with conditional breakpoint capabilities. The system provides state inspection interfaces for examining processor state, memory contents, and application variables during stopped execution. Runtime logic executes configuration files with support for conditional breakpoints triggered by runtime data values, performance metrics, or error conditions. The system enables multi-processor synchronization with coordinated breakpoint handling across processor arrays, dynamic reconfiguration of processor configurations during stopped execution, and performance profiling at breakpoint locations. Breakpoint conditions can be defined at multiple granularity levels for computational graphs and dataflow applications. The system supports interactive debugging with step-through execution control and real-time modification of execution parameters.