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Memristor-based summator, driving method and electronic equipment

A driving method and memristor technology, applied in the field of electronics, can solve the problems of small delay, complex structure, difficult integration, etc., and achieve the effect of eliminating alignment work, reducing computing delay, and being easy to integrate.

Pending Publication Date: 2022-07-08
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, the method of designing N-bit adder with IMP has been studied, but the operation of N-bit adder is still relatively complicated
Adders based on threshold gates and MeMOS cannot achieve storage and computing integration, and their structures are more difficult to integrate than IMP-based adders
Lauren Guckert proposed MAD and proposed an adder based on MAD, which has a small delay but a complex structure
There is no adder that can realize the integration of storage and calculation, and has the characteristics of easy integration, low delay and small integration area.

Method used

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  • Memristor-based summator, driving method and electronic equipment
  • Memristor-based summator, driving method and electronic equipment
  • Memristor-based summator, driving method and electronic equipment

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] refer to figure 1 , figure 1This embodiment is a schematic structural diagram of a memristor-based adder. like figure 1 As shown, the memristor-based adder includes:

[0041] 1T1R array, N peripheral circuits, the 1T1R array includes a first 1T1R sub-array, a second 1T1R sub-array, a third 1T1R sub-array, a fourth 1T1R sub-array, and a fifth 1T1R sub-array arranged in sequence, the first 1T1R sub-array The 1T1R sub-array, the second 1T1R sub-array, the third 1T1R sub-array, and the fourth 1T1R sub-array respectively include N 1T1R units, and the fifth 1T1R sub-array includes N+1 1T1R units. The 1T1R unit includes a memristor and a MOS transistor, and the bottom electrode of the memristor is connected to the source or drain of the MOS transistor;

[0042] The drain or source of the MOS transistor in each 1T1R unit of each 1T1R sub-array is connected to the word line of the corresponding column, and the gate of the MOS transistor in each 1T1R unit of each 1T1R sub-arr...

Embodiment 2

[0096] refer to Figure 9 , Figure 9 This embodiment provides a driving method for an adder, which can be used to drive the memristor-based adder described in Embodiment 1 above. The following describes the steps of the driving method for the adder. To elaborate:

[0097] Step S901, according to the logic value of the memristor in the i-th 1T1R unit of the first 1T1R sub-array, the logic value of the memristor in the i-th 1T1R unit of the second 1T1R sub-array, and the logic value of the third 1T1R sub-array The logic value of the memristor in the i-th 1T1R cell, determines the logic value of the memristor in the i+1-th 1T1R cell of the third 1T1R subarray, 1≤i≤N-1, and according to the first 1T1R The logic value of the memristor in the Nth 1T1R cell of the subarray, the logic value of the memristor in the Nth 1T1R cell of the second 1T1R subarray, and the logic value of the memristor in the Nth 1T1R cell of the third 1T1R subarray The logic value of the memristor determin...

Embodiment 3

[0149] This embodiment provides an electronic device, which stores a computer program, and when the computer program runs on a processor, executes the method for driving an adder provided in Embodiment 2 above.

[0150] The electronic device provided in this embodiment can implement the steps of executing the method for driving the adder provided in Embodiment 2, which is not repeated here to avoid repetition.

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Abstract

The invention provides an adder based on a memristor, a driving method and electronic equipment, the adder based on the memristor comprises a 1T1R array and N peripheral circuits, the 1T1R array comprises a first 1T1R sub-array, a second 1T1R sub-array, a third 1T1R sub-array, a fourth 1T1R sub-array and a fifth 1T1R sub-array which are arranged in sequence, the first 1T1R sub-array, the second 1T1R sub-array, the third 1T1R sub-array and the fourth 1T1R sub-array respectively comprise N 1T1R units, the fifth 1T1R sub-array comprises N + 1 1T1R units, and each 1T1R unit comprises a memristor and an MOS (Metal Oxide Semiconductor) tube. Through the memristor-based adder provided by the invention, a calculation result is non-volatile, carry operation is realized through the CCAU, calculation time delay is reduced, and in addition, the main body area of the adder is relatively small and the adder is easy to integrate.

Description

technical field [0001] The present invention relates to the field of electronic technology, and in particular, to a memristor-based adder, a driving method and an electronic device. Background technique [0002] Existing computer systems are mainly designed using the Von Neumann structure. The Von Neumann structure has the characteristics of separation of storage and computing, resulting in bottlenecks such as "storage wall" and "power consumption wall", which seriously restrict the development of computing system performance. A memristor is a basic circuit element that describes the relationship between charge and flux. Its resistance state changes with the applied excitation (voltage or current), and the resistance state remains unchanged when the excitation is removed. The memristor logic proposed according to the characteristics of the memristor can realize the integration of storage and computing. A new computing system designed using memristor logic is expected to bre...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/505G11C13/00
CPCG06F7/505G11C13/004G11C13/0069
Inventor 王义楠李清江王伟傅星智王伟贺李智炜徐晖刁节涛陈长林刘森宋兵刘海军于红旗王玺步凯王琴曹荣荣
Owner NAT UNIV OF DEFENSE TECH
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