Six-stage pipeline processor based on RISC-V instruction set

A RISC-V, pipeline technology, applied in the direction of concurrent instruction execution, machine execution device, climate sustainability, etc., can solve the problem of low processor performance

Pending Publication Date: 2022-07-08
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The depth of existing pipelines in my country is relatively shallow, most of them have

Method used

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  • Six-stage pipeline processor based on RISC-V instruction set
  • Six-stage pipeline processor based on RISC-V instruction set
  • Six-stage pipeline processor based on RISC-V instruction set

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Embodiment Construction

[0039]The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are intended to explain the present invention and should not be construed as limiting the present invention.

[0040] see Figure 1 to Figure 7 , the present invention provides a six-stage pipeline 1 architecture based on the RISC-V instruction set:

[0041] It includes a six-stage pipeline 1, a first register 2, a data memory 3 and an instruction memory 4. The six-stage pipeline 1 includes an instruction fetch module 11, a decoding module 12, a distribution module 13, a transmission module 14, an execution module 15 and a write back Module 16, the instruction fetch module 11, the decoding module...

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Abstract

The invention relates to the field of computer components, in particular to a six-level assembly line processor based on an RISC-V instruction set, which comprises a six-level assembly line, a first register, a data memory and an instruction memory, and is characterized in that an instruction fetching module, a decoding module, a distribution module, a transmitting module, an execution module and a write-back module of the six-level assembly line are connected in sequence; the data memory is connected with the execution module and the write-back module, the first register is connected with the distribution module and the write-back module, and the instruction memory is connected with the instruction fetching module. The characteristic of out-of-order execution of double-instruction decoding emission is achieved, and a reference model is provided for superscalar parallel design of the RISC-V processor. And a Gshare branch prediction circuit is provided, so that the branch prediction success rate is improved. The register is renamed, so that assembly line cavitation caused by reading after writing and writing after writing is remarkably reduced. And a complete branch prediction failure repair circuit is provided, so that the time loss caused by branch prediction failure is reduced.

Description

technical field [0001] The invention relates to the field of computer components, in particular to a six-stage pipeline processor based on a RISC-V instruction set. Background technique [0002] In the traditional classification of computer architecture, processor applications are divided into three fields, namely: server field, program counter field and embedded field. At present, in the field of server and program counter, the x86 architecture is a well-deserved giant, and no instruction set architecture can shake its monopoly. [0003] In recent years, with the rapid development of Internet of Things technology, the market has an increasing demand for low-power, high-performance processors used in smart terminals. How to reduce the cost and power consumption while meeting the performance requirements of the intelligent terminal on the processor is a relatively popular research direction. At present, this direction is mainly monopolized by ARM's Cotex-A series processor ...

Claims

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Application Information

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IPC IPC(8): G06F9/38
CPCG06F9/3867Y02D10/00
Inventor 吕治宽黄逸轩
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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