Networking layout method and device, equipment and storage medium

Abstract

The invention provides a networking layout method and device, equipment and a storage medium, and belongs to the field of integrated circuit chip design, and the method comprises the steps: carrying out the networking segmentation of a design file according to a networking file, and obtaining a networking segmentation result, the networking segmentation result is used for describing corresponding distribution positions, logic groups and connection relations among the hypergraph nodes in the logic array system; obtaining physical networking data of the logic array; distributing each logic group in the networking segmentation result based on the physical networking data to obtain at least one first layout; and setting the first layout with the minimum interconnection cost as a final layout. Through the processing scheme provided by the invention, the number of transfer routing paths, interconnection cost and communication delay are reduced, and the communication efficiency of the verification system is improved, so that the verification frequency is improved, and the verification process is accelerated.

Description

technical field [0001] The invention relates to the field of integrated circuit chip design, in particular to a networking layout method, device, equipment and storage medium. Background technique [0002] When the resources consumed by the user chip design logic are greater than the upper limit of an programmable logic device (FPGA), the user chip design needs to be divided into multiple parts, each part is called a logic group, and each logic group will be assigned to On a corresponding FPGA, groups communicate with each other through physical interconnections between the FPGAs. The existing division process is to directly divide the user chip design into N groups, and then randomly assign the N groups to the networking of the verification system of M logic arrays. If there is no direct physical connection between the logical connections (communication signals) between the groups, adjust the path of the logical signal so that it can be routed through other intermediate FP...

AI Technical Summary

Problems solved by technology

In this way, logical groups with a large number of external connections are assigned to the edge of the network topology, which is equivalent to a connection key group and a hotspot group, which are assigned to the edge, such as the side of a matrix-type verification array. This will not only generate more routing transfers, but also need to cross more interconnection lines, thereby increasing the interconnection cost and signal transmission delay, and leading to low communication efficiency. For example, other connected packets need long-distance communication to arrive. edge, and retrieve the result of the signal processing from the edge

Moreover, the loose arrangement method may occupy more FPGAs, and the edge of the system array needs to be routed through the relay FPGA. The relay path occupies the FPGA that could not be used, which not only increases unnecessary device loss, It also wastes resources

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