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Semiconductor device, power module, and method for manufacturing semiconductor device

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as difficulty in insulation resistance, and achieve the effect of improving insulation resistance

Pending Publication Date: 2022-07-26
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, it is difficult to improve the insulation resistance of current semiconductor devices.

Method used

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  • Semiconductor device, power module, and method for manufacturing semiconductor device
  • Semiconductor device, power module, and method for manufacturing semiconductor device
  • Semiconductor device, power module, and method for manufacturing semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0055] figure 1 It is a plan view showing the inside of the semiconductor device according to the first embodiment. figure 2 is along figure 1 Sectional view of I-II. The second conductor plate 2 is separated from the first conductor plate 1 . A plurality of semiconductor elements 3 are mounted on the first conductor plate 1 . The semiconductor element 3 has the control electrode 4 and the front surface electrode 5 on the front surface, and has the back surface electrode 6 on the back surface. When the semiconductor element 3 is a MOSFET, the control electrode 4 is a gate electrode, the front surface electrode 5 is a source electrode, and the back surface electrode 6 is a drain electrode.

[0056]The back electrodes 6 of the plurality of semiconductor elements 3 are connected to the first conductor plate 1 . One relay board 7 is mounted on the second conductor board 2 . In addition, a plurality of relay boards 7 may be mounted on the second conductor board 2 .

[0057]...

Embodiment approach 2

[0080] Figure 23 It is a plan view showing the inside of the semiconductor device according to the second embodiment. A cutout portion 26 is provided in the sealing material 15 . The notch part 26 is arrange|positioned between the 1st conductor board 1 and the 2nd conductor board 2 which were isolate|separated. The cut surfaces of the first conductor plate 1 and the second conductor plate 2 are exposed at the cutout portion 26. However, when the power module is constructed, the semiconductor device is covered with the peripheral encapsulation material 30, so that the first conductor plate 1 and the second conductor plate 2 can be improved. Insulation of conductor plate 2 .

[0081] Next, the manufacturing method of the semiconductor device which concerns on Embodiment 2 is demonstrated. Figure 24 , 26 , 28 , 30 , 32 , 34 , 36 , 38 , and 40 are plan views showing manufacturing steps of the semiconductor device according to the second embodiment. Figure 25 , 27 , 29 , 3...

Embodiment approach 3

[0091] Figure 42 It is a plan view showing the inside of the semiconductor device according to the third embodiment. Figure 43 is along Figure 42 Sectional view of I-II. The source conductor block 28 is connected to the second conductor plate 2 . The source pads 29 of the plurality of semiconductor elements 3 are connected to the second conductor plate 2 by wires 31 . The first relay pad 10 and the second relay pad 11 of the relay substrate 7 are insulated from the second conductor plate 2 and the source conductor block 28 by the insulating film 9 . In addition, the source conductor block 28 may be plural.

[0092] The source conductor block 28 is exposed from the second main surface S2 of the encapsulation material 15 and functions as a source control electrode. As a result, the second conductor plate 2 can be fixed at the source potential, so that the floating portion can be eliminated. Therefore, even when the semiconductor device is turned on and off at a high spe...

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PUM

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Abstract

Provided are a semiconductor device, a power module, and a method for manufacturing the semiconductor device that can easily improve insulation tolerance. The second conductor plate (2) is separated from the first conductor plate (1). The back surface electrodes of the plurality of semiconductor elements (3) are connected to the first conductor plate. A relay substrate (7) is provided on the second conductor plate. The relay substrate (7) has a plurality of first relay pads (10) and a second relay pad (11) connected to the plurality of first relay pads. The control electrodes (4) of the plurality of semiconductor elements are respectively connected to the plurality of first relay pads. The first conductor block (13) is connected to the surface electrodes (5) of the plurality of semiconductor elements (3). The second conductor block (14) is connected to the second relay pad (11). The first conductor plate (1) is exposed from the first main surface (S1) of the sealing material (15). The second conductor plate (2) is not exposed from the first main surface (S1). The first and second conductor blocks (14) are exposed from the second main surface (S2).

Description

technical field [0001] The present invention relates to a semiconductor device, a power module, and a method for manufacturing the semiconductor device. Background technique [0002] In a module using SiC MOSFETs, since it is difficult to increase the area of ​​SiC MOSFETs, in order to increase the current capacity, a plurality of chips are connected in parallel. A semiconductor device has been proposed in which a plurality of semiconductor elements and wiring elements are bonded to the same conductor plate, and control electrodes of the plurality of semiconductor elements are connected in parallel via circuit patterns of the wiring elements (for example, see Patent Document 1). [0003] Patent Document 1: International Publication No. 2020 / 110170 [0004] The wiring element is provided with an oxide film for insulation on the front and back surfaces. In the current semiconductor device, this oxide film ensures insulation between the conductor plate at the drain potential ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498H01L23/31H01L21/56H01L21/60
CPCH01L23/49816H01L23/49844H01L23/3114H01L23/49811H01L24/81H01L24/85H01L21/56H01L2224/81H01L2224/85H01L23/49562H01L23/49575H01L23/49517H01L23/49548H01L23/49503H01L2224/0603H01L2224/73265H01L2224/45139H01L2224/45144H01L2224/45015H01L24/45H01L2224/32245H01L2924/181H01L2224/92247H01L2224/85205H01L2224/45014H01L2224/29101H01L2224/83801H01L2224/8384H01L2924/15747H01L2224/84205H01L2224/37124H01L2224/37147H01L24/37H01L24/29H01L2224/8484H01L2224/84801H01L24/84H01L2924/13091H01L2224/33181H01L24/33H01L2224/48155H01L24/49H01L2224/49109H01L24/73H01L24/48H01L24/32H01L24/83H01L2224/04026H01L2224/04042H01L23/3107H01L23/3135H01L25/115H01L2924/00014H01L2924/20755H01L2924/2076H01L2924/00012H01L2924/014H01L2924/00H01L2224/73221H01L2924/37001H01L25/0655H01L25/50H01L2224/48227H01L2224/29084
Inventor 中田洋辅佐藤祐司横山吉典
Owner MITSUBISHI ELECTRIC CORP