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Method for measuring overlay mark and overlay error

A technology of overlay marks and mark patterns, which is applied in the field of semiconductors, can solve the problems that overlay marks are prone to defects, affect the accuracy of overlay error measurement, and reduce product yield, so as to increase the density of patterns and reduce differences , the effect of improving the quality

Pending Publication Date: 2022-08-05
CHANGXIN MEMORY TECH INC
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AI Technical Summary

Problems solved by technology

[0003] However, overlay marks are prone to defects during the formation process, which affects the measurement accuracy of subsequent overlay errors, thereby reducing the yield of products

Method used

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  • Method for measuring overlay mark and overlay error
  • Method for measuring overlay mark and overlay error
  • Method for measuring overlay mark and overlay error

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Embodiment Construction

[0024] It can be seen from the background art that the overlay marks are prone to defects during the formation process. The analysis found that the main reason is that the overlay marks belong to the low-density pattern area relative to the array area. Based on the etching load effect, the reactive ions in the pattern-intensive area are The active ingredients are consumed quickly, and the etching rate is reduced; on the contrary, the etching rate of the pattern sparse area is higher, resulting in the problems of over-etching and different degrees of etching.

[0025] For example, Figure 1-Figure 4 A schematic diagram of the structure corresponding to each step in a method for manufacturing an overlay mark is shown. Specifically, refer to figure 1 , a spin-coatable dielectric layer 43 is coated on the first mask layer 41 and the second mask layer 42 . refer to figure 2 , the spin-coatable dielectric layer 43 is etched back to expose the top surface of the second mask layer ...

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Abstract

The embodiment of the invention relates to the field of semiconductors, and provides an overlay mark and an overlay error measurement method, which at least can improve the quality of the overlay mark, thereby improving the measurement accuracy of the overlay error and improving the yield of products. The overlay mark comprises a first pattern layer and a second pattern layer, the first pattern layer is formed on the substrate before the second pattern layer, and orthographic projections of the first pattern layer and the second pattern layer on the substrate are staggered; each of the first pattern layer and the second pattern layer comprises a plurality of mark patterns which are arranged at intervals and a plurality of noise patterns which are arranged between the adjacent mark patterns at intervals; the feature size of the noise pattern is smaller than that of the mark pattern; the mark pattern of the first pattern layer and the mark pattern of the second pattern layer can be matched to obtain an overlay error.

Description

technical field [0001] The present disclosure belongs to the field of semiconductors, and in particular relates to an overlay mark and a method for measuring overlay error. Background technique [0002] In order to improve the integration of the device, it is usually necessary to sequentially transfer the patterns on each photomask to the substrate through a multi-layer lithography process. Therefore, the positions between the upper and lower patterns can be aligned by means of overlay marks. In other words, the overlay error obtained by the overlay mark can reflect the alignment deviation between different layers. [0003] However, defects are easily generated during the formation of the overlay marks, which affects the measurement accuracy of subsequent overlay errors, thereby reducing the yield of products. SUMMARY OF THE INVENTION [0004] The embodiments of the present disclosure provide an overlay mark and an overlay error measurement method, which is at least benef...

Claims

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Application Information

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IPC IPC(8): H01L23/544H01L21/66G03F7/20G03F9/00
CPCH01L23/544H01L22/12H01L22/20G03F7/70633G03F9/708H01L2223/54426
Inventor 盛薄辉
Owner CHANGXIN MEMORY TECH INC
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