Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the following steps: providing a substrate; a first material layer is formed on the substrate, the first material layer is patterned, a first pattern is formed in the first material layer, first grooves are formed in the two sides of the first pattern in the first direction, and a first preset area on the substrate is exposed out of the first grooves; performing a first doping process on the first preset region along the first groove; filling a first dielectric layer in the first groove, and continuing to pattern the first material layer so as to expose a second preset region on the substrate; performing a second doping process on the second preset region; the substrate is thermally treated. According to the invention, before the second doping process, the first doping process is carried out at the two ends of the channel region to form the first type of doped region which is not activated, so that ions injected by the second doping process can be blocked by the first type of doped region and cannot be diffused to the channel region, the overlapping area of the gate structure and the doped region is reduced, and tunneling leakage current is reduced.

Description

technical field [0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for fabricating a semiconductor structure and a semiconductor structure. Background technique [0002] With the continuous development of integrated circuit technology, the number of semiconductor devices integrated in a single chip continues to increase, and the size of transistors in the semiconductor device also continues to decrease. [0003] As the size of the transistor continues to decrease, when the voltage at the gate and drain overlap is large, the electrons in the silicon near the cross section of the overlap region undergo band-band tunneling between the valence band and the conduction band to form a current. This current It is called gate-induced drain leakage (GIDL). As the thickness of the gate oxide layer gradually becomes thinner, the tunneling current intensity between the gate and the drain increases sharply, which affects the per...

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Problems solved by technology

As the thickness of the gate oxide layer gradually becomes thinner, the tunneling current intensity between the gate and the drain increases sharply, which affects the performance of the semiconductor

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