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Semiconductor integrated circuit

An integrated circuit and semiconductor technology, applied in amplifiers with semiconductor devices/discharge tubes, amplifiers with only semiconductor devices, logic circuit connection/interface layout, etc., can solve the problem of output signal waveform deterioration, output signal load change, MOS transistor voltage is difficult and other problems

Inactive Publication Date: 2005-02-02
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, even for input signals of the same amplitude, especially when the common level becomes low, the voltages of the gate terminals of the MOS transistors TN1 and TN2 with respect to the respective source terminals are difficult to exceed their own thresholds
Thus, the waveform of the output signal deteriorates, for example, a problem arises that the load of the output signal varies with respect to the input signal
Moreover, if the common level is so low that the voltages of the gate terminals of the MOS transistors TN1 and TN2 relative to the respective source terminals do not exceed the threshold voltage at all, the differential amplifier will not even operate at all.

Method used

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  • Semiconductor integrated circuit
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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0034] image 3 The structure of the semiconductor integrated circuit 10 according to Embodiment 1 of the present invention is shown. The semiconductor integrated circuit 10 is an amplifying circuit, which includes: a differential amplifier circuit 12 for amplifying the voltage difference of the input signals A and B applied to the nodes N1 and N2; a common level detection circuit 14; and a bias voltage generation circuit 16 for generating a bias voltage suitable for the differential amplifier 12 based on the detected common level. difference amplifier 12 with figure 1 The structure shown is the same, and what is applied to the gate terminal of the MOS transistor TN3 is not a fixed voltage but a bias voltage generated by the bias voltage generating circuit 16 .

[0035] The input signals A and B are theoretically inverse signals, if the signal A is high level, then the signal B is low level at this time. If signal A is low, then signal B is high at this time. The high leve...

Embodiment 2

[0049] Figure 6 It is a configuration diagram showing another example of the bias voltage generating circuit 16 . In this example, the operational amplifier is deleted, and the output of the differential amplifier 20 is directly used as a bias voltage Vb to be applied to the gate terminal of its own MOS transistor TN3 and the gate terminal of the MOS transistor TN3 of the differential amplifier 12, 20. In addition , others are the same as Figure 5 The circuit shown is the same.

[0050] As mentioned above, an increase in the common level Vc has the effect of causing the voltage at the node N to decrease. However, since the voltage of the node N is applied as the bias voltage Vb to the gate terminal of the MOS transistor TN3, even if the common level Vc rises, the amount of current flowing through the MOS transistor TN3 decreases, and the voltage drop of the node N is suppressed instead.

[0051] In addition, the drop of the common level Vc has the function of causing the ...

Embodiment 3

[0056] Figure 7 It is a configuration diagram showing still another embodiment of the bias voltage generation circuit 16 . In this example, the MOS transistors TP2 and TN2 are deleted, and the voltage of the drain terminal of the MOS transistor TP1 is applied to the operational amplifier, and Figure 7 The transistor size (=gate width / gate length) of the MOS transistor TN11 in is Figure 5 half of the MOS transistor TP2, other than that, the other with Figure 5 The circuit shown is the same.

[0057] The bias generating circuit 16 with Figure 5 The same operation is performed by the circuit, when the common level Vc changes, the bias voltage Vb changes, so that the voltage of the drain terminal of the MOS transistor TP1 is maintained at the reference voltage Vref. When the common level Vc rises, the bias voltage Vb falls, and when the common level Vc falls, the bias voltage Vb rises. Moreover, the bias generating circuit 16 is connected with Figure 5 Compared with th...

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Abstract

The invention aims to provide a semiconductor integrated circuit capable of outputting a signal whose level changes in response to an input signal even though the input common level of the input signal fluctuates. A semiconductor integrated circuit includes a differential amplifier, a common level detection circuit which detects a common level of input signals A and B, and a bias generation circuit which generates a bias voltage to be applied to a gate terminal of a MOS transistor that is a constant-current power source of the differential amplifier based on the detected level.

Description

technical field [0001] The present invention relates to semiconductor integrated circuits for amplifying input signals. Background technique [0002] figure 1 A conventional well known difference amplifier is shown. This differential amplifier is composed of p-channel MOS transistors TP1, TP2 and n-channel MOS transistors TN1, TN2, TN3. [0003] The MOS transistor TP1 has a source terminal receiving a power supply voltage VDD, and a drain terminal and a gate terminal connected to each other. The MOS transistor TP2 has a source terminal receiving the power supply voltage VDD, a drain terminal connected to the node N, and a gate terminal connected to the gate terminal of the MOS transistor TP1. The MOS transistor TN1 has a drain terminal connected to the drain terminal of the MOS transistor TP1 and a source terminal connected to the node M. MOS transistor TN2 has a drain terminal connected to node N and a source terminal connected to node M. MOS transistor TN3 has a sourc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0175H03F3/45
CPCH03F3/45708H03F2203/45401H03F3/45
Inventor 内木英喜近藤晴房
Owner MITSUBISHI ELECTRIC CORP