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Electricity induction soure-drain extended zone MOS transistor and its making method

A MOS transistor, source-drain extension region technology, applied in transistors, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as limiting driving current, improving lithography accuracy, and achieving threshold voltage optimization, solving manufacturing problems, process Simple and easy effects

Inactive Publication Date: 2005-08-17
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the length of the induced source-drain extension region of this structure is still restricted by the lithography precision, which limits the further improvement of the driving current.

Method used

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  • Electricity induction soure-drain extended zone MOS transistor and its making method
  • Electricity induction soure-drain extended zone MOS transistor and its making method
  • Electricity induction soure-drain extended zone MOS transistor and its making method

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Embodiment Construction

[0097] 1. Inductive source-drain extension region MOS transistor structure

[0098] Such as figure 2 As shown, the MOS transistor structure of the induced source-drain extension region, the gate of the induction source-drain region is served by an inverted polysilicon sidewall 23, the source-drain extension region is generated by electrical induction of the inverted polysilicon, and the channel region is located between the two inverted polysilicon sidewalls between two inverted polysilicon sidewalls; the gate electrode is a T-shaped polysilicon gate 21, and there is a silicon dioxide isolation layer 22 between the gate electrode and the inverted polysilicon sidewall; the gate electrode and the inverted polysilicon sidewall are both There is an oxide layer; the channel region and the source and drain extension regions are doped independently.

[0099] 2. Preparation process of MOS transistor structure with inductive source-drain extension region

[0100] The main process ste...

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Abstract

The present invention provides an inductive source-drain extended region MOS transistor structure and its preparation method. The structure adopts the inverted polysilicon side wall as inductive source-drain extended region gate electrode, the inductive source-drain extended region is produced by utilizing inverted polysilicon electric induction, at the same time the channel region is formed by utilizing invented polysilicon side wall; between gate electrode and invented polysilicon side wall the silicon dioxide isolating layer is formed, and under the gate electrode and inverted polysilicon side wall there are oxide layers, and the channel region and inductive source-drain extended region are independently doped.

Description

technical field [0001] The invention relates to a MOS transistor structure and a preparation method thereof in the technical field of ultra-large-scale integrated circuits (ULSI). Background technique [0002] At present, the proportional reduction of device feature size is rapidly approaching the physical limit, and the channel length has been reduced to 10nm. In order to ensure the electrical performance of the device, other parameters of the device, especially the PN junction depth of the induced source-drain extension region of the device must also be reduced in proportion. . For example, when the gate length is less than 20nm, in order to obtain good short-channel effect and DIBL effect, the PN junction depth of the device's induction source-drain extension region should be less than 10nm, and it is very difficult to manufacture such a shallow PN junction. The inductive source-drain extension region below 20nm is one of the urgent problems to be solved at present. [...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/786
Inventor 刘文安刘金华黄如张兴
Owner SEMICON MFG INT (SHANGHAI) CORP